Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2000-03-20
2003-06-17
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S117000
Reexamination Certificate
active
06581019
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to computers and, more particularly, to testing computer systems fabricated on an integrated circuit. A major objective of the present invention is to provide computer-system-on-a-chip designs with enhanced built-in testability.
Much of modern progress is associated with the increasing prevalence of computers, including embedded controllers as well as general-purpose computers. A typical computer includes a processor, memory, and peripherals that communicate with each other over a system bus. In many computers, the processor, memory, and some peripherals are embodied in separate integrated circuits. However, with advances in integrated-circuit manufacturing technology allowing millions of transistors on an integrated circuit, it is now practical to build computer systems on an integrated circuit (chip). Instead of assembling separate integrated circuits on a printed-circuit board, computers can be designed by assembling functional blocks on an integrated-circuit layout.
Testing of complex integrated circuits, such as single-chip computers is an essential and formidable task. While the functional block designs are often well characterized, they are subject to manufacturing defects. In addition, each circuit design represents a novel arrangement of functional blocks that requires testing both for design integrity and for defects in the connections between function blocks.
The prior art provides a default method for testing a computer system. A test program can be run on the computer processor, which can write to peripherals coupled to the system bus and then read from the system bus to determine if the expected results occur. While much can be accomplished with this approach, it is typically not effective at testing non-system-bus connections between on-chip peripherals or between on-chip peripherals and off-chip devices. Likewise, on-chip functions that rely on non-system-bus inputs, e.g., communications from a modem, can be hard to evaluate. Accordingly, several approaches to augmenting this processor-based testing approach have been considered.
One prior-art “multiplex-to-pins” approach is to multiplex the input-output ports of functional blocks to provide controllability of input and observability of outputs. This allows for external test equipment to test the non-system bus connections. A major problem with this multiplex-to-pins approach is that it precludes many possible test combinations. Tests requiring more than one use of a pin at a time cannot be performed. If a pin is used to access an internal connection, its normal use is precluded. Likewise, if a pin is multiplexed to more than one internal connection, only one of these may be accessed at a time. Even with careful assignment of pins to internal connections, the restrictions on test combinations can be prohibitive. Typically, only a single peripheral is tested, not its connections to the rest of the system, thus degrading a key goal of the test. In addition, the multiplex-to-pins approach requires flexible test hardware to map peripheral test patterns to pins—since that mapping varies from device to device.
In addition, this multiplex-to-pins approach becomes less practical as the number of internal connections increases relative to the number of pins. Multiplexing internal connections to pins consumes routing resources, and the inter-blocks routes tend to be very costly in terms of area. Moreover, non-test application performance can be adversely affected not only by the additional multiplexers, but also by the parasitic capacitances along the paths between the input-output ports and the pins.
Scanning approaches introduce data serially and read out the results serially, thus avoiding much of the routing complexity of the multiplex-to-pins approach. JTAG (“Joint Test Action Group”) is a standardized test-interface specification for the scanning. The JTAG specification requires a five-pin interface to test equipment. These pins are “serial test-data in” (TDI), “serial test-data out” (TDO), “test clock” (TCK), “test reset” (TRST), and “test-mode select” (TMS). Thus, the number of pins required for testing using the prevailing scan approaches is small and fixed. Thus, problems with routing and test-pin count are vastly reduced compared to the multiplex-to-pins approach.
The vast majority of complex chips use a “fulls scan” approach to test for manufacturing faults. In the full-scan approach, all registers, including those internal to functional blocks, are arranged in a serial shift chain. Typically, the order of registers in a full-scan serial-shift chain is not determined as part of the design process, but as an automated post-design procedure. Due to the functionally arbitrary order and large number of registers involved, functional testing using the full-scan approach is impractical. Instead, functional testing is achieved by simulation, and the full scan is used to check for manufacturing faults. Furthermore, scan approaches are destructive in nature, since old state data will be shifted out as new data is shifted in.
The simulation used for design validation and the full scan used for finding manufacturing faults are performed before an integrated circuit is integrated into a system. Configurations not anticipated in the simulation are not tested. Latent manufacturing defects that become overt during use (e.g., due to gradual electro-migration) may not be detected by the full scan. In addition, in view of the large amount of shifting required, the full scan can be very time consuming.
The prior-art also reaches a more limited “peripheral-scan” (also known as “partial-scan” or “scan-wrapper”) approach. In the peripheral-scan approach, non-system-bus functional block ports are multiplexed to latches or registers arranged in a serial shift chain. Test data can be shifted in from external test equipment, a clock cycle run to clock data into the peripheral and capture outputs, and then the data can be shifted out to the external test equipment. Thus, the peripheral-scan approach can be used for functional testing. However, scanning data in and out is still quite time consuming.
The approaches discussed above all involve difficult tradeoffs. While the full-scan is relatively comprehensive in the components it can test, it is impractical to use it for functional testing. On the other hand, while a peripheral-scan allows for functional testing, the range of components that are tested is more limited than it is for the full-scan approach. The multiplex-to-pins approach is faster, but is costly in terms of routing resources.
A bus-access approach couples external testing equipment a system bus. Each module to be tested has a test harness with test registers. Each test register can be associated with a module input or outputs. During testing, these registers are coupled to the system bus so that they can be accessed by the external test equipment. Such a test approach is disclosed by Arm Limited in “AHB Example AMBA System Technical Reference Manual”. This document was obtained in the year 2000 the Arm, Limited website at www.arm.com. The document is copyrighted 1999, and no publication date is given.
The bus-access approach is faster than the scan approaches and consumes fewer routing resources than does the multiplex-to-pins approach. However, Arm's implementation still requires thirty-six dedicated pins, which is costly in terms of packages and board area.
The bus-access, scan and the multiplex-to-pin approaches share many limitations. A salient limitation is the requirement for dedicated testing equipment. The testing equipment is expensive. The requirement of the external testing makes it impractical to test circuits once they are in use, which, in turn, makes it difficult to test in the context of signals associated with normal use.
More generally, the bus-access, scan, and multiplex-to-pins approaches all require a test mode in which conditions are very difficult from normal operation. Functional modules are not performing their normal functions and n
Bapst Mark V.
Caesar Robert J.
Hoff Marc S.
Koninklijke Philips Electronics , N.V.
West Jeffrey R
Zawilski Peter
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