Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2003-02-11
2003-10-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S230080
Reexamination Certificate
active
06639822
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a dynamic random access memory (RAM) and a semiconductor device and more particularly, the invention relates to an effective technique using a so-called one cross point method where a dynamic memory cell is arranged at a cross point of a word line and a bit line.
According to a search conducted after this invention was made, some publications which might be related to the technology of the present invention, to be described later as an open bit line type (or one cross point method) dynamic RAM, were found, including Japanese Patent Laid-Open No. 206991/1988 (related art 1, hereinafter), Japanese Patent Laid-Open No. 13290/1989 (related art 2, hereinafter), U.S. Pat. No. 5,608,668 (related art 3, hereinafter), and Japanese Patent Laid-Open No. 41081/1993 (related art 4, hereinafter). According to related arts 1 and 2, one sense amplifier is fitted into a pitch for two bit lines by positioning sense amplifies alternately, based on the open bit line method (one-cross point method). According to related arts 3 and 4, there is provided a circuit achieving, based on an electrical model which is substantially the same as a bit line, for achieving a reference voltage required for an operation by a sense amplifier provided at an end portion in a case where sense amplifiers are positioned alternately for more efficient use of a chip area, as in the related arts 1 and 2.
SUMMARY OF THE INVENTION
Due to process variations, which will increase with an increase in micronization of elements, operational conditions are expected to differ largely between a sense-amplifier at the end portion and a sense amplifier to which bit lines are equipped on both sides. Thus, according to reviews by the inventor hereof, it was found that the need for operational stability will become more and more important. In the related arts 1 and 2, no considerations are made for the arrangement at the end portion in a case where sense amplifiers were arranged alternately with respect to the bit lines.
Further, a cost reduction has been desired for the dynamic RAM (DRAM, hereinafter). In order to achieve such a cost reduction, reducing the chip sizes may be the most effective answer. The size of a memory cell has been reduced by promoting its micronization. However, it will be necessary to further reduce the cell size by changing the operating method of memory arrays from now on. By changing the memory array operating method from the two cross point method to the one cross point method, the cell size can be reduced 75% ideally based on the same design rule. In order to achieve a cell size reduction more effectively, the inventor hereof considered effective uses of memory cells provided at the end portion and the reduction of their area of occupation when the sense amplifiers are arranged alternately in the memory array according to the one cross point method as described above.
It is an object of the present invention to provide a DRAM and a semiconductor device based on the one cross point method which can achieve an improvement of operational margins and a reduction of the chip area. The above and other objects and new features of the present invention will be apparent from the description in this specification and the accompanying drawings.
An outline of a typical aspect of the present invention disclosed herein may be described in brief as follows. There is provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines and the plurality of word lines, the plurality of memory mats being placed in the direction of a bit line, and a sense amplifier array including a plurality of latch circuits are provided in areas between the memory mats placed in the bit line direction, respectively, a pair of input/output nodes of which are connected to half of the bit lines provided in the memory mats. In this case, for a general memory mat, other than both end portions in the bit line direction, the word lines in any one of the memory mats are activated, while, for end memory mats provided on both end portions in the bit line direction, the word lines of both memory mats are activated together.
REFERENCES:
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5886943 (1999-03-01), Sekiguchi et al.
patent: 6125070 (2000-09-01), Tomishima
patent: 6272066 (2001-08-01), Ooishi
patent: 63206991 (1988-08-01), None
patent: 6413290 (1989-01-01), None
patent: 541081 (1993-02-01), None
Arai Koji
Fujisawa Hiroki
Takemura Riichiro
Antonelli Terry Stout & Kraus LLP
Elms Richard
Hitachi , Ltd.
Nguyen Hien
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