Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-09-15
1996-01-16
Sikes, William L.
Static information storage and retrieval
Addressing
Sync/clocking
365196, 365203, 327 51, G11C 800, G11C 700
Patent
active
054854300
ABSTRACT:
A method and circuit is provided for reading a memory array which utilizes multiple clocking signals during one read cycle to enable a dynamic sense amplifier to read data from the memory array. A dynamic sense amplifier is connected to an input line, a complementary input line, and a latch. A first equilibrating signal is input into the sense amplifier, followed thereafter by a first clocking signal. The first clocking signal enables the sense amplifier to read data on the input line and complementary input line. While the sense amplifier reads the data, the sense amplifier is isolated from the input and complementary input lines. Based upon the data read by the sense amplifier, an output state is provided for the latch. After reading the data, the sense amplifier is reconnected to the input and complementary input lines. A second clocking signal then enables the sense amplifier to read the data on the input and complementary input lines a second time, and the sense amplifier is isolated from the input and complementary input lines. The output state of the latch may or may not change based upon the data read by the sense amplifier the second time.
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Hill Kenneth C.
Jorgenson Lisa K.
Nguyen Tiep H.
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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