Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-07-25
2003-11-25
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S143000, C365S226000
Reexamination Certificate
active
06653880
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon Japanese Patent Application No. 2000-227247 filed on Jul. 27, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device including a plurality of circuit blocks operating at different power source voltages.
2. Description of the Related Art
Microcomputers in general supply a single power source voltage to each internal circuit unit and give a common reset signal to operate it. As the internal circuits constituting the microcomputer have become smaller, in scale in recent years, the power source voltage applied to the internal circuits is divided in some cases into plural systems.
In other words, when miniaturization of the internal circuits reaches a certain level, the power source voltage must be set to a low level in view of a withstand voltage of each element formed in a chip. For example, a circuit portion corresponding to a core unit performing a principal function of the microcomputer is caused to operate at 3 V and an interface unit generating a signal to be outputted to external devices is caused to operate at 5 V in conformity with signal levels of peripheral circuits connected outside the microcomputer.
FIG. 4
illustrates an example of the microcomputer devised by inventors of the present invention. A microcomputer
1
includes therein a 5 V power source circuit
2
and a 3 V (3.3 V, in practice) power source circuit
3
. The 5 V power source circuit
2
is so constituted as to generate a 5 V power source upon receiving power from a power supply terminal Vcc. The generated 5 V power is supplied to the 3 V power source circuit
3
, a 3 V reset generation circuit
4
, a 5 V reset generation circuit
5
, a 5 V system circuit unit
6
and an input/output terminal unit
7
. The 3 V power is supplied to the 3 V reset generation circuit
4
and a 3 V system circuit unit
8
.
3 V and 5 V reset signals are generated at the 3 V and 5 V reset generation circuits
4
and
5
, and are supplied to the circuit unit of each system. In other words, the 5 V power source is supplied as an operation power source to the 3 V reset generation circuit
4
, and the 3 V reset signal is outputted when the rise of the 3 V power source is sensed.
Signals inputted from outside to the microcomputer
1
are given from the input/output terminal unit
7
to the 3 V system circuit unit
8
through the 5 V system circuit unit
6
. Signals outputted from the 3 V system circuit unit
8
to outside are outputted to the input/output terminal unit
7
through the 5 V system circuit unit
6
. The input/output terminal unit
7
communicates to external devices to input signals from the external devices and output the signals from the 3 V system circuit unit
8
and the 5 V system circuit unit
6
. Incidentally, a level conversion circuit, not shown, is interposed between the 3 V system circuit unit
8
and the 5 V system circuit unit
6
to change a signal level between 3 V-signal and 5 V-signal.
However, when the reset signal is supplied to each circuit unit, the following problems develop if each reset time is different.
FIG. 5
is a timing chart that shows an example of a power-ON reset sequence in the microcomputer
1
. When the 5 V power source is first activated and reaches a reset terminating voltage, the 5 V reset signal becomes inactive, so that reset of the 5 V system circuit unit
6
is terminated (see FIGS.
5
(
a
) and (
b
)). The 5 V system reset signal remains indefinite for a limited period in which the 5 V power source reaches the operation start voltage of the 5 V system (see FIG.
5
(
b
)).
On the other hand, the rise of the 3 V power source is likely to be slower than that of the 5 V power source because the 3 V power source is generated on the basis in the generation of the 5 V power source. In such a case, a timing at which the 3 V power source reaches reset terminating voltage is likely to occur after the 5 V power source reaches the reset terminating voltage (see FIGS.
5
(
c
) and (
d
)). Since the 3 V reset generation circuit
4
starts operating upon receiving the supply of the 5 V power source, the 3 V system reset signal remains indefinite until the 5 V power source reaches 5 V system operation start voltage (see FIG.
5
(
d
)).
Incidentally, scale of the ordinate (voltage) is magnified in FIG.
5
(
c
) and the rise is slow. Therefore, the rise of the 3 V power source is shown rising linearly as in FIG.
5
(
c
). When the rise waveform of the 3 V power source is macroscopically observed in practice, however, it has a waveform similar to that of the rise of the 5 V power source.
The output signal of the 3 V system circuit unit
8
remains indefinite until the 3 V power source reaches 3 V system operation start voltage. For the period in which the 3 V system reset signal is active after reaching the operation start voltage the output signal is set at an initial value (voltage at the time of the reset operation; “L” in FIG.
5
((
e
)). Therefore, the output signal of the 5 V system circuit unit
6
is indefinite during the period in which the output signal of the 3 V system circuit unit
8
is indefinite although the 5 V system reset signal has already been terminated (refer to arrow in FIG.
5
(
f
)). The output level of the input/output terminal unit
7
that receives this signal is also indefinite.
As described above, when the voltage applied to the 3 V system circuit unit
8
is still below the operation start voltage in the situation where the reset is released in the 5 V system circuit unit
6
, the signal that becomes active (such as “H”) might be outputted to outside through the 5 V system circuit unit
6
before the reset of the core unit of the microcomputer
1
is finished. When the active signal is outputted unintentionally, a wrong operation may occur in the system in which the microcomputer
1
functions as the central control unit.
When microcomputers
1
having the same performance are mass-produced and exist in a system, the reset sequence in each of the overall microcomputers
1
does not always attain the same sequence as the one shown in
FIG. 5
due to variance of the discrete microcomputers
1
. The rise on the 3 V power source may be faster than the rise of the 5 V power source depending on the discrete microcomputers
1
, for example. When such variance of discrete microcomputers
1
during mass-production is taken into consideration, fail-safe measure for securing the reset sequence becomes very important in microcomputers operating at power sources of a plurality of systems.
SUMMARY OF THE INVENTION
In view of the problems described above, the present invention aims at providing a semiconductor integrated circuit device capable of preventing an unnecessary signal from being outputted to outside before reset is terminated when a plurality of circuit blocks operate at different power source voltages.
In the semiconductor integrated circuit device according to the present invention, a reset signal to be given to an input/output interface unit for exchanging input/output signals with external devices is generated on the basis of a reset signal having the longest reset period among reset signals given to a plurality of circuit blocks operating at different power source voltages, respectively.
Preferably, the reset signal to be given to the input/output interface unit is generated by OR between a plurality of reset signals, and an OR element outputting the OR signal is operated by the same power source as the power source for the input/output interface unit.
In other words, reset of the input/output interface unit is not terminated until a reset signal having the longest reset period among the reset signals given to respective circuit blocks is terminated. Therefore, when a plurality of circuit blocks is disposed in series with the input/output interface unit, a reset period of the reset signal supplied to a circuit block closest to the input/output interface unit
Ishihara Hideaki
Obata Hiroyuki
Denso Corporation
Nguyen Minh
Posz & Bethards, PLC
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