Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-09-14
2003-02-04
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06515500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus of testing and analyzing a complementary metal oxide semiconductor (CMOS) integrated circuit.
2. Description of the Related Art
Japanese Unexamined Patent Publication (Kokai) No. 8-271584, Japanese Unexamined Patent Publication (Kokai) No. 9-211088, U.S. Pat. No. 5,392,293, U.S. Pat. No. 5,519,333, and U.S. Pat. No. 5,889,408 disclose testing (I
DDQ
testing) using a drain-to-drain quiescent power supply current (I
DDQ
) of a CMOS integrated circuit.
In I
DDQ
testing, measures the quiescent power supply current of a CMOS integrated circuit, is measured, and a good or defective of the CMOS integrated circuit is determined by using the measured current. Note that a CMOS integrated circuit under test is also called a device under test (DUT).
A quiescent power supply current I
DDQ
includes a leakage current (intrinsic leakage current) flowing even in a good device and a defect current caused by a defect. That is, a quiescent power supply current I
DDQ
, (hereinafter also called a quiescent power supply current I
Q
) can be expressed by the summation of the intrinsic quiescent power supply current I
F
and defect current I
D
and can be shown by the following formula (1):
I
Q
=I
F
+I
D
(1)
The intrinsic leakage current I
F
can be expressed by the summation of the leakage current (FET leakage current) I
T
generated due to the structure of a metal oxide semiconductor field effect transistor (MOSFET) and the leakage current (circuit leakage current) caused due to a circuit operation.
The circuit leakage current is generated by an analog circuit, pull-up current, bus collision, etc. Generation of the circuit leakage current is however avoided when I
DDQ
testing for measuring the quiescent power supply current I
Q
and therefore it can be disregarded. Therefore, the following formula (2) can represent the defect current I
D
:
I
D
=I
Q
−I
T
(2)
In the I
DDQ
testing, the FET leakage current I
T
of the CMOS integrated circuit under test is unknown and therefore estimated by some method or another. The good or defect of the CMOS integrated circuit is judged by using the measured quiescent power supply current I
Q
.
The main defect current I
D
in the quiescent power supply current I
Q
is current generated by internal shorts among gates, sources, drains, and well of the FET and a bridging between interconnection patterns. The value of the defect current I
D
depends on the power supply voltage and equivalent resistance value.
FIG. 1
is a graph of the relative frequency distribution of the maximum I
DDQ
(the maximum value of the quiescent power supply current I
Q
) in two types of integrated circuits as an example. The maximum I
DDQ
of an abscissa is broken down into 0 to 100 &mgr;A, 100 to 200 &mgr;A, . . . , 700 to 800 &mgr;A, and 800 &mgr;A or more.
The effective gate length Leff of the type A and B CMOS integrated circuits is 0.5 &mgr;m. A maximum I
DDQ
of more than 30 &mgr;A is shown. The distribution shown in
FIG. 1
substantially corresponds to the distribution of the defect current I
D
.
Further, A. E. Gattiker and W. Maly, “Toward Understanding ‘Iddq-Only’ Fails”, in
Int. Test Conf.
, pp.174-183, IEEE, 1998, states that there is an indirectly generated defect current, in addition to the defect current generated directly by the bridging. This indirect defect current is generated because when a potential of a signal line falls between the power-supply voltage and the ground potential for some reason or another, the p type MOSFET and n type MOSFET driven by this signal line become on in state at the same time, and a penetration current flows.
It is necessary to apply a different voltage to the two ends of a bridge forming a defect in order to cause generation of the defect current I
D
.
Since it is impossible to set the potential required for all presumed failures all at once, a test signal of a test pattern prepared by an automatic test pattern generator (ATPG) or a test signal of a test pattern for a function test is applied and the quiescent power supply current I
Q
measured when a terminal becomes the necessary potential. Note that a measurement point for measuring the quiescent power supply current I
Q
is called as a strobe (strobe point).
The strobe point (defect detection strobe point) which can detect a defect differs according to the cause of the defect.
Since bridging between the power supply line for supplying a power supply voltage V
D
and a ground line has no relation with the potential of the signal line, the defect is detected at all strobe points and the defect current becomes the same.
Note that there are few defect detection strobe points which can detect bridging of interconnections between cells. Further, the number of defect detection strobe points which can detect a short of the MOSFET in the cell is a levels between the two.
According to A. Keshavarzi, K. Roy, and C. F. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs”, in
Int. Test Conf
., pp. 146-155, IEEE, 1997; A. Ferre and J. Figueras, “On Estimating Bounds of the Quiescent Power Supply Current for I
DDQ
Testing”, in
VLSI Test Sym
., pp. 106-111, IEEE, 1996; and P. C. Maxwell and J. R. Rearick, “Estimation of Defect-Free IDDQ in Submicron Circuits Using Switch Level Simulation”, in
Int. Test Conf
., pp. 882-889, IEEE, 1998, the leakage current (EFT leakage current) I
T
of a defect-free normal MOSFET can be classified based on the ON/OFF state of the MOSFET, the current path, etc.
FIG. 2
is a graph showing a classification of the leakage current of a MOSFET.
FIG. 2
shows a feeding power route, causes of occurrence, conduction conditions, and an approximation formula of the leakage current with respect to cases L
1
, to L
3
.
In the case L
1
, the feeding power route is between a well and base (substrate), the cause of occurrence is an inverse bias of a pn junction, and the conduction condition is an ON state.
In the case L
2
, the feeding power route is between a drain and well, the cause of occurrence is the inverse bias of the pn junction, and the conduction condition is an OFF state.
In the case L
3
, the feeding route is between the drain and source, the cause of occurrence is a weak inverse, and the conduction condition is an OFF state.
The leakage current of the case L
1
is always generated if the well and base are inverse biases and is constant regardless of the strobe (strobe point).
The leakage current of the case L
2
is generated in a case where the MOSFET is in an OFF state and the drain thereof is connected to the power supply line and/or the ground line.
The leakage currents of the case L
3
is generated in a case where the MOSFET is in an off state and the drain and the source thereof are connected to the power supply line and/or the ground line.
If the leakage currents of the cases Li (i =1 to 3) in each MOSFET in a CMOS integrated circuit are averaged for each case, the leakage currents L
N1
and L
N1
in per n type MOSFET and p type MOSFET are found.
The FET leakage current IT can be expressed by the following formula (3) using the numbers N
N1
and N
P1
of the n type MOSFETs and the p type MOSFETs in which the leakage current of the case L
1
has been generated:
I
T
=
∑
F
=
1
3
(
N
Ni
×
I
Mi
+
N
Pi
×
I
Pi
)
(
3
)
FIG. 3
is a chart illustrating the distribution of the maximum I
DDQ
in an CMOS integrated circuit and shows the frequency distribution for every 0.1 &mgr;A. The effective gate length Leff of the CMOS integrated circuit is 0.5 &mgr;m.
In
FIG. 3
, a CMOS integrated circuit having a maximum I
DDQ
of less than 1 &mgr;A is judged as good and a CMOS integrated circuit having a maximum I
DDQ
of 1 &mgr;A or more is judged as defective.
Note that the broken line shows a curve of an average value of 0.2 &mgr;A and a standard deviation &sgr; of 0.14 &mgr;A. In a good CMOS integrated circuit having a maximum I
DDQ
of below 1 &mgr;A, the distribution of the FE
Kananen Ronald P.
Nguyen Jimmy
Rader & Fishman & Grauer, PLLC
LandOfFree
Method and apparatus of testing and analyzing CMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus of testing and analyzing CMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus of testing and analyzing CMOS... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3146708