Image writing control unit having memory area for image

Details Image writing control unit having memory area for image Image writing control unit having memory area for image

1990-06-25

1994-01-04

Richardson, Robert L.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395164, 395400, 345191, G06F 1520

Patent

active

052768007

ABSTRACT:
A control unit includes a first frame buffer and a second frame buffer as the memory area, a microprocessor, a shift circuit, a shift number register and a mask pattern generating circuit. An image data signal is output from the microprocessor. Shifting of respective words of the image data is performed by the shift circuit in compliance with a shift number signal output from the shift number register, for writing the words of the image data into the first and second frame buffers from desired bit positions corresponding to the shift numbers. Mask pattern signals nullifying bits, except the bits corresponding to the image data in output data of the shift circuit, are output from the mask pattern generating circuit. Selection between a high order side portion and a low order side portion of each word of the image data to be written into the frame buffers is performed by the least significant bit of an address signal. The address value input into the first buffer is incremented by "1" in an adder. The first frame buffer is accessed by address line output from the adder from which the least significant bit is removed, while the second frame buffer is accessed by address line output from the microprocessor. Access to address N or N+1 in the first frame buffer and address N+1 or N in the second frame buffer is thereby achieved.

REFERENCES:
patent: 4839826 (1989-05-01), Urushibata
patent: 4945495 (1990-07-01), Ueda
patent: 4985848 (1991-01-01), Pfeiffer et al.
patent: 5095446 (1992-03-01), Jingu

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