Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-09-12
2003-12-09
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
Reexamination Certificate
active
06658732
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of printed circuit boards (“PCBs”). More particularly, the present invention relates to a method of making higher impedance traces on a low impedance circuit board.
2. Discussion of Related Art
The common types of PCBs are a double-sided PCB and multi-layered PCB. A double-sided PCB includes conductive planes formed on the both sides of an insulation layer. A multi-layered PCB includes a plurality of conductive planes and insulation layers. In a multi-layered PCB, an insulation layer is typically formed in between conductive planes. The multi-layered PCB can have three or more conductive planes. The conductive planes refer to signal trace layers, power planes, or ground planes.
FIG.
1
A and
FIG. 1B
show a multi-layered PCB
100
.
FIG. 1A
shows an illustration of a cross-sectional view of PCB
100
.
FIG. 1B
shows an illustration of a top view of PCB
100
of FIG.
1
A.
Referring to
FIG. 1A
, PCB
100
includes signal traces
190
,
193
,
195
, and
197
and conductive planes
110
and
155
. PCB
100
also includes insulation layers
105
,
130
,
140
, and
160
formed in between the signal traces and conductive planes, a blind via
102
, and a buried via
103
.
Signal traces
195
and
197
are formed on a bottom side of insulation layer
105
. Blind via
102
is formed in insulation layer
105
. Conductive reference plane
110
is formed on insulation layer
105
and over blind via
102
. Blind via
102
is a plated-through hole, which can be used to couple electrically conductive reference plane
110
with signal trace
197
. Insulation layer
130
is formed on conductive reference plane
110
. Buried via
103
and signal traces
193
are formed in insulation layer
130
. Buried via
103
is a plated-through hole, which can be used to couple electrically one of the signal traces
193
with conductive reference plane
110
. Insulation layer
140
is formed on insulation layer
130
and signal traces
193
. Signal traces
195
and
197
can be used to interconnect electronic components (not shown) on the bottom side of insulation layer
105
. Signal traces
193
can be used to interconnect electronic components on insulation layer
130
. Signal traces
190
can be used to interconnect electronic components on insulation layer
160
. As shown in
FIG. 1B
, signal traces
190
can have varying shapes and sizes.
Insulation layer
105
provides insulation between signal traces
195
and
197
and conductive reference plane
110
. Insulation layer
130
and
140
provide insulation between conductive reference planes
110
and
155
. Insulation layer
160
provides insulation between conductive reference plane
155
and signal traces
190
. Conductive reference plane
155
is a ground plane, which can be used as a common electrical circuit return. Conductive reference plane
110
is a power plane, which can be used to provide specified potential to the signal traces.
In recent years, double-sided and multi-layered PCBs have become increasingly thinner to meet the demand of consumers for smaller and more compact electronic products. One way used to make thinner PCBs is by reducing the thickness of the insulation layers between the conductive planes. However, reducing the thickness of the insulation layers of the signal traces can affect the characteristic impedance of the signal traces on the PCBs.
The characteristic impedance of a signal trace is primarily determined by inductance and capacitance as shown in Equation (1):
Z
0
=
L
C
(
1
)
in which Z
0
is the characteristic impedance of the signal trace, L is the inductance per unit length of the signal trace, and C is the capacitance per unit length of the signal trace. Furthermore, the capacitance per unit length of the signal trace is generally expressed as shown in Equation (2)
C
=
KS
d
(
2
)
in which C is the capacitance per length of the signal trace, K is the dielectric constant, S is the electrode plate size (primarily width of the signal trace), and d is the distance between two electrode plates (the separation distance between the signal trace and the nearest conductive plane).
When these two equations are combined, the resulting equation is as shown in Equation (3)
Z
0
=
Ld
KS
(
3
)
According to Equation (3), if the inductance per unit length of the signal trace (L), dielectric constant (K), and the width of the signal trace (S) remain constant, the characteristic impedance of the signal trace can decrease by decreasing d, which is the separation distance between the signal trace and the nearest conductive plane.
Typically, the reduction of the separation distance is beneficial because such reduction reduces cross-talk and lessens the effects of electromagnetic interference (“EMI”) on the signal traces. However, in certain applications, some signal traces, such as video signal traces, require higher impedances to match properly with electronic components, such as video displays, that operate with higher impedances.
According to Equation (3), the characteristic impedance of a signal trace can be increased by keeping the factors L, K, and S constant and increasing d, which is the separation distance between the signal trace and the conductive reference plane that is located closest to the signal trace. This, however, increases the thickness of an insulation layer thereby causing the characteristic impedance of all other signal traces on the insulation layer to be increased.
Another way to increase the characteristic impedance of a signal trace, according to Equation (3), is to decrease the width of the signal trace (S). However, decreasing the width of the signal trace may significantly increase the cost of fabricating a PCB and may violate manufacturing standards.
REFERENCES:
patent: 4685033 (1987-08-01), Inoue
patent: 5519176 (1996-05-01), Goodman et al.
patent: 5633479 (1997-05-01), Hirano
patent: 5719750 (1998-02-01), Iwane
patent: 6180215 (2001-01-01), Sprietsma et al.
patent: 6184478 (2001-02-01), Imano et al.
patent: 6218631 (2001-04-01), Hetzel et al.
patent: 6239485 (2001-05-01), Peters et al.
Electrical Design and Simulation of High Density Printed Circuit Boards, IEEE Transactions Advanced Packaging, vol. 22, No. Aug. 1999. pp. 416-423 by Swirbel et al.
Arbes Carl J.
Blakely , Sokoloff, Taylor & Zafman LLP
LandOfFree
Method of making higher impedance traces on low impedance... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making higher impedance traces on low impedance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making higher impedance traces on low impedance... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3143021