Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-09-22
2003-02-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S199000, C438S218000, C438S221000, C438S433000, C438S524000
Reexamination Certificate
active
06514833
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a plurality of semiconductor devices, e.g., MOS and CMOS transistors and integrated circuits containing such transistors, on a common semiconductor substrate, with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m and under.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
A conventional approach for forming a plurality of active devices in or on a common semiconductor substrate, e.g., as in the case of forming CMOS devices comprising PMOS and NMOS transistors in spaced adjacency, involves division of a starting material, i.e., a semiconductor substrate of suitable characteristics, into active regions where the transistors are to be formed, and field dielectric regions that electrically isolate adjacent active regions.
According to current technology, the starting material may comprise a lightly-doped p-type epitaxial layer (“epi” layer) grown on a heavily-doped p-type substrate. The low resistance of the heavily doped substrate is needed to minimize susceptibility to latch-up; whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p- and n-wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
The use of very thin epi layers, i.e., about 4 &mgr;m thick, is made possible by performing the isolation processing by means of shallow trench isolation (STI) techniques rather by high temperature local oxidation of silicon (“LOCOS”). The former technique advantageously minimizes up-diffusion of p-type dopant from the more heavily-doped substrate into the lightly-doped epi layer. In addition, and critical for fabrication of devices with a design rule of 0.25 &mgr;m and below. STI allows for closer spacing of adjacent active areas by avoiding the “bird's beak” formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from the active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
Conventional STI methodology comprises initially forming a nitride masking layer over the surface of the substrate to differentiate the active (i.e., source/drain) regions and the field (i.e., isolation) regions, with a thin barrier oxide layer preliminarily formed beneath the nitride layer for relieving stress during oxidation. After nitride layer formation, a source/drain mask is utilized for defining the active areas in a resist layer formed over the nitride layer. After masking, the nitride layer is etched away from the field (isolation) areas while the resist protects the active areas. The STI process continues the source/drain etch through the nitride and barrier oxide layers into the underlying silicon; whereas, in conventional LOCOS processing, etching is stopped at the barrier oxide layer. After a trench of a desired depth is etched into the silicon, the source/drain resist mask is removed, and a thin liner oxide layer is formed as to round the top and bottom comers of the trench to prevent gate oxide reliability problems and improve subsequent trench fill. Next, a thick oxide layer is deposited which fills the active regions and covers the nitride layer over each active region. The thick oxide layer is then planarized to remove all the oxide over the active regions leaving the isolation trenches filled with oxide. The nitride is then stripped off the active regions.
Following division of the substrate, typically a silicon wafer, into active and isolation regions, the wafer is further subdivided into n-well and p-well regions in which the p- and n-channel transistors, respectively, will be formed. In a true “twin-tub” process both the n- and p-wells are implanted, rather than leaving the p-type epi layer untouched as the p-well. Consequently, each well profile can be independently tailored in the lightly-doped epi layer to optimize n- and p-channel transistor performance. Well doping is kept sufficiently low such that body effect (gamma) and source/drain-to-substrate capacitance do not degrade the transistors, but high enough such that off-state leakage current due to source-to-drain punch-through does not limit the minimum geometry transistors.
Typically, a retrograde-structured n-well is initially formed, by dopant implantation (e.g., phosphorus ions) at a sufficiently high energy to place the impurity concentration peak deep in the (silicon) substrate, while covering the p-well areas with resist. After stripping the resist and a rapid, low-temperature furnace anneal to activate the dopant, the n-well areas are masked with resist for performing the n-channel field implant. The n-channel field implant, typically boron ions, is implanted sufficiently deep to also serve as the p-well implant and increases the threshold of the n-channel transistors to improve isolation between adjacent active areas within the p-well. The process continues with a series of additional implants for setting the threshold (i.e., turn-on) voltage of each of the n- and p-channel transistors, gate formation, and transistor source/drain, source/drain extension implants, including post-implantation annealing, e.g., rapid thermal annealing (RTA) for implant activation and lattice damage relaxation.
While the above-described STI technology is considerably more amenable to fabrication of devices with a design rule of 0.18 &mgr;m and below than LOCOS methodology, the close proximity of the n- and p-wells in the vicinity of the narrow trench is problematic in terms of an increased likelihood of lateral interdiffusion of dopant impurities between the oppositely doped wells. particularly diffusion of boron dopant from the p-type well to the n-type well in the case of silicon, resulting in counterdoping of at least the proximal portions of adjacent wells. Moreover, notwithstanding the use of RTA rather than high temperature furnace-type post-implantation annealing for minimizing such dopant diffusion/interdiffusion, the extent of lateral dopant diffusion/interdiffusion and attendant deleterious effects can be significant, disadvantageously resulting in counterdoping of adjacent wells, reduction of isolation between adjacent active device regions, and degradation of other device characteristics.
Accordingly, there exists a need for improved semiconductor methodology for fabricating MOS and CMOS transistors and integrated circuit devices comprising a plurality of such transistors which does not suffer from the above-described drawbacks associated with the conventional methodology. There exists a need for an improved MOS/CMOS fabrication process fully compatible with conventional process flow which provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above-mentioned problems and drawbacks attendant upon conventional processing for forming submicron-dimensioned MOS and CMOS transistors for use in high-density semiconductor integrated circuit devices. In accordance with embodiments of the present invention, prior to filling of the isolation trench or groove with a dielectric
Ishida Emi
Ng Che-Hoo
Advanced Micro Devices , Inc.
Lytle Craig P.
Smith Matthew
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