Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-05-01
2003-06-03
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
69, 69
Reexamination Certificate
active
06573186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device, and more particularly, to a method for forming a plug of a semiconductor device that improves characteristic of the semiconductor device and its structure.
2. Background of the Related Art
Generally, a poly plug is formed using polysilicon in a DRAM and a logic device. Recently, with the reduction of the design rule, a chemical mechanical polishing (CMP) process is used to form a poly plug, instead of an etch back process.
Two methods for forming a poly plug using CMP process have been suggested.
One method is to form a poly plug using the CMP process after contact etching.
The other is a method for forming a line poly plug by depositing polysilicon and then etching it by the CMP process. In this method, the CMP process may be performed to form a line poly plug directly after a later process is performed on a wordline pattern and polysilicon is deposited thereon. In this case, a height difference of a plug may occur due to a density difference of a lower structure (gate pattern). To minimize such height difference, after forming polysilicon, polysilicon in a portion where lower pattern density is high may partially be removed by an etching process and then a plug is formed by the CMP process.
The first related art method for forming a plug of a semiconductor device will be described with reference to the accompanying drawings. In this method, a poly plug is formed within a contact hole using the CMP process.
FIGS. 1
a
to
1
f
are sectional views showing the first related art method for forming a plug of a semiconductor device.
As shown in
FIG. 1
a
, a first polysilicon film
11
and a cap insulating film
12
for a wordline are sequentially formed on a semiconductor substrate
10
in which a cell region and a peripheral region are defined.
The first polysilicon film
11
and the cap insulating film
12
are selectively removed to densely form the wordline in the cell region and sparsely form the wordline in the peripheral region.
An insulating film
13
is formed on an entire surface of the semiconductor substrate
10
including the cap insulating film
12
. A first photoresist (not shown) is then deposited on the insulating film
13
and patterned to expose the cell region only.
Insulating film spacers
13
a
are formed at both sides of the cap insulating film
12
and the first polysilicon film
11
by performing etch-back process in the exposed cell region, and the first photoresist is removed.
As shown in
FIGS. 1
b
and
1
c
, an inter layer dielectric (ILD) film
14
is formed on the entire surface of the semiconductor substrate
10
and then planarized by the CMP process.
As shown in
FIG. 1
d
, a second photoresist (not shown) is deposited on the entire surface and then patterned by exposure and developing processes to define a contact region.
The ILD film
14
is selectively removed using the patterned photoresist as a mask to partially expose the surface of the semiconductor substrate
10
. Thus, a contact hole
15
is formed and the second photoresist is removed.
As shown in
FIGS. 1
e
and
1
f
, a second polysilicon film
16
is formed on the entire surface including the contact hole
15
, and the CMP process is performed using the ILD film
14
as an end point to form a poly plug
16
a
within the contact hole
15
. The poly plug
16
a
electrically connects an upper structure with the semiconductor substrate.
The second method for forming a poly plug by an etching process after forming a polysilicon line of a damascene structure will now be described.
FIGS. 2
a
to
2
c
are sectional views showing the second related art method for forming a plug of a semiconductor device.
As shown in
FIG. 2
a
, a first polysilicon film
21
and a cap insulating film
22
for a wordline are sequentially formed on a semiconductor substrate
20
in which a cell region and a peripheral region are defined.
The first polysilicon film
21
and the cap insulating film
22
are selectively removed to densely form the wordline in the cell region and sparsely form the wordline in the peripheral region.
An insulating film
23
is formed on an entire surface of the semiconductor substrate
20
. A photoresist (not shown) is then deposited on the insulating film
23
and patterned to expose the cell region only.
Insulating film spacers
23
a
are formed at both sides of the cap insulating film
22
and the first polysilicon film
21
by performing etch-back process in the exposed cell region, and the photoresist is removed.
As shown in
FIGS. 2
b
and
2
c
, a second polysilicon film
24
is formed on the entire surface of the semiconductor substrate
20
, and the CMP process is performed using the cap insulating film
22
as an end point to form a poly plug
24
a
in a space between the insulating film spacers
23
a
of the cell region and around the wordline of the peripheral region.
At this time, it is difficult for the end point to be detected during the CMP process due to density difference of the wordline pattern in the cell region and the peripheral region. For this reason, the first polysilicon film
21
and the poly plug
24
a
in the peripheral region are damaged, thereby generating a step difference between the poly plug
24
a
of the cell region and the poly plug
24
a
of the peripheral region.
To solve the above problem according to the second related art method for forming a plug of a semiconductor device, the third related art method for forming a plug of a semiconductor device will be described with reference to
FIGS. 3
a
to
3
d.
FIGS. 3
a
to
3
d
are sectional views showing the third related art method for forming a plug of a semiconductor device.
As shown in
FIG. 3
a
, a first polysilicon film
31
and a cap insulating film
32
for a wordline are sequentially formed on a semiconductor substrate
30
in which a cell region and a peripheral region are defined.
The first polysilicon film
31
and the cap insulating film
32
are selectively removed to densely form the wordline in the cell region and sparsely form the wordline in the peripheral region.
An insulating film
33
is formed on an entire surface of the semiconductor substrate
30
in which the wordline is formed. A photoresist (not shown) is then deposited on the insulating film
33
and patterned to expose the cell region only.
Insulating film spacers
33
a
are formed at both sides of the cap insulating film
32
and the first polysilicon film
31
by performing etch-back process in the exposed cell region, and the photoresist is removed.
As shown in
FIGS. 3
b
and
3
c
, a second polysilicon film
34
is formed on the entire surface of the semiconductor substrate
30
. A photoresist (not shown) is then deposited on the entire surface and patterned by exposure and developing processes.
The second polysilicon film
34
on the wordline densely formed in the cell region is removed using the patterned photoresist as a mask, and the photoresist is removed.
As shown in
FIG. 3
d
, the CMP process is performed using the cap insulating film
32
as an end point to form a poly plug
34
a
in a space around both the insulating film spacers
33
a
of the cell region and the wordline of the peripheral region.
However, the aforementioned related art methods for forming a plug of a semiconductor device have several problems.
First, the CMP process of polysilicon causes a height difference of the poly plug due to pattern density of the lower structure (wordline pattern).
The third related art method to solve the first problem has a problem in ensuring a process margin according to the formation of polysilicon and the etch-back process. The third related art method also has a problem in detecting the end point essentially required in the CMP process.
Furthermore, in the third related art method, a photolithography process is additionally performed to minimize the height difference of the poly plug. Thus, the process becomes more complicated and costly.
SUMMARY OF THE INVENTION
Accor
Chaudhuri Olik
Hyundai Electronics Industries Co,. Ltd.
Kebede Brook
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