Write to read switching time trim circuit

Details Write to read switching time trim circuit Write to read switching time trim circuit

2000-11-07

2003-02-18

Holder, Regina N. (Department: 2651)

Dynamic magnetic information storage or retrieval

General recording or reproducing

Specifics of the amplifier

C360S046000, C360S061000, C360S062000

Reexamination Certificate

active

06522492

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to disk circuits and, more particularly, to a method and apparatus for reading information from a magnetic disk.
BACKGROUND OF THE INVENTION
Conventional magnetic storage devices include a magnetic transducer or “head” suspended in close proximity to a recording medium, for example a magnetic disk, having a plurality of concentric tracks. The transducer is supported by an air-bearing slider mounted to a flexible suspension. The suspension, in turn, is attached to a positioning actuator. During normal operation, relative motion is provided between the head and the recording medium as the actuator dynamically positions the head over the desired track. The relative movement provides an air flow along the surface of the slider facing the medium, creating a lifting force. The lifting force is counterbalanced by a predetermined suspension load so that the slider is supported on a cushion of air, Air flow enters the “leading” end of the slider and exits from the “trailing” end. This air is used to prevent the head from contacting the disk, resulting in damage.
Writing data is typically performed by applying a current to the coil of the head so that a magnetic field is induced in an adjacent magnetic permeable core, with the core transmitting a magnetic signal across any spacing and protecting coating of the disk to magnetize a small pattern or digital bit of the medium within the disk. Reading of the information in the disk is performed by sensing the change in magnetic field of the core as the transducer passes over the bits in the disk. The changing magnetic field induces a voltage or current in the inductively coupled coil. Alternatively, reading of the information may be accomplished by employing a magneto-resistive (MR) sensor, which has a resistance that varies as a function of the magnetic field adjacent to the sensor. In order to increase the amplitude and resolution in reading the bits, the MR sensor is typically positioned on the slider as close to the disk as possible. Connected to these heads or sensors are read circuits which amplify the recorded data and eliminate noise. However, recently, some manufacturers of these MR sensors have switched from MR heads which employ a constant current source to MR heads which employ a constant voltage source.
A typical pre-amplifier for reading information from the read head includes a differential pair of output signals corresponding to reading information from each side of the read head. A problem with this differential output signal is the offset between the differential output signal. Importantly, this offset is directly related to the write/read time which is the time to transfer from a write state to a read state. More particularly, if the offset is great, the write to read time is long and if the offset is small the write to read time is small. Consequently, it has been necessary to provide a circuit to compensate for this offset.
FIG. 2
illustrates such an offset compensation circuit where a current mirror circuit
202
provides current to the base of transistor
226
. The collector to emitter current of transistor
226
which is controlled by this base current is the current through the MR head
228
. The voltage across resistor
121
is compared with the voltage across resistor
224
by transconductance device
230
and the current output from transconductance device
230
is used to form a voltage on capacitor
232
. Since G
M
is equal to I
E
divided by V
IN
, and since the capacitor
232
is typically large because it was external to the chip, G
M
could be large to result in small offset voltages, namely V
IN
.
However, since it is desirable to have capacitor
232
move on chip, this requires a smaller capacitor
232
and consequently G
M
should be correspondingly smaller. However, a small G
M
dictates that the offset voltage will be large in order to satisfy the above equation. Larger offset voltages as discussed above increases the write to read time and is correspondingly undesirable. Thus, there is a need for a write to read switching time trim circuit which will take into consideration the effect of placing the above-mentioned capacitor on chip and the corresponding effects of having the capacitor a relatively-small size. It is important to maintain a small write to read time, and as a consequence, it is important to maintain a minimum offset between the differential output signals.
SUMMARY OF THE INVENTION
The present invention provides a read to write switching time trim circuit that minimizes offset between differential outputs. More particularly, the write to read switching time trim circuit of the present invention minimizes the read to write time required when a hard disk drive system is switching between write mode to a read mode.


REFERENCES:
patent: 5278700 (1994-01-01), Sutliff et al.
patent: 6157241 (2000-12-01), Hellums
patent: 6169393 (2001-01-01), Hashimoto

Affiliated with

Also associated with

Rating

Write to read switching time trim circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Write to read switching time trim circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write to read switching time trim circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3140841