Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-10-27
2003-11-18
Saras, Steven (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000, C345S066000
Reexamination Certificate
active
06650307
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of driving a display panel of a plasma display panel (referred to as PDP hereinafter) or the like, and a panel display apparatus employing the method. More particularly, the present invention relates to a method of driving a display panel in which displays with gray scale are performed by weighting each subframe to change the discharge and light emission period for display, and a panel display apparatus employing same.
Recently, in the field of display apparatus, demands for a thinner, larger-screen, and higher-resolution display apparatus are increasing information to be displayed and conditions under which display apparatuses are installed are becoming more diversified, and a display apparatus to meet these demands and cope with the diversification is required. There are several types of thin display apparatuses such as LCDS, fluorescent display tubes, ELs, PDPs, and so forth. In a fluorescent display tube, EL, or PDP, gray scale display is realized, in general, by dividing a display frame into plural subframes, weighting each subframe period, and displaying each bit of the gray scale data using a corresponding subframe. Though the following explanation will use a PDP as an example, the detailed explanation of a PDP itself is omitted here because it has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. 9-160525 by the same applicants, and the gray scale representation by the subframe method and the power control relating to the present invention will be explained generally.
FIG. 1
is a block diagram showing the general structure of a general PDP display apparatus. In a panel
1
, plural X electrodes and Y electrodes are arranged adjacently in turn and plural address electrodes are arranged in the direction that runs at a right angle to the aforementioned electrodes. The plural X electrodes are connected commonly, and are connected to an X driver
2
. Each of the plural Y electrodes is connected to a Y driver
3
. The plural address electrodes are connected to an address driver
4
. A power source
5
supplies power to the X driver
2
, the Y driver
3
, and the address driver
4
.
Though it is assumed that the input image signals are RGB digital signals, in some cases they may be analog signals and, in such a case, they are converted into digital data by an A/D converter. The input image signal is amplified by digital operations in a gain control circuit
11
and stored temporarily in a frame memory
13
by a data converter
12
. At this time, the input image signal is loaded into the display plane of the frame memory
13
according to a subframe format, which will be explained later, read from each display plane according to the subframe to be displayed, and supplied to the address driver
4
as address data. The data converter
12
counts the number of lit pixels for each subframe when storing the input image signal into the frame memory
13
, calculates the display load ratio, and then sends them to a driver controller
14
. The display load ratio relates to the sum of light emission intensity of all cells, that is, the total number of discharge pulses for light emission (radiation pulses) in the entire panel (referred to briefly as a number of pulses in some cases hereinafter). The driver controller
14
supplies a certain gain coefficient to the gain control circuit
11
, where the input image signal is multiplied by the gain coefficient. The gain coefficient is stored in a ROM or the like as a value fixed in advance, or can be set by a control that adjusts the display luminance. When the gain coefficient is set by a luminance control circuit using a variable resistor, it can be changed externally, but it is not changed automatically according to the input image signal.
A power control circuit
15
calculates the total number of pulses for a display frame based on the values of voltage and current supplied by the power source
5
and the display load ratio supplied by the driver controller
14
, determines the number of radiation pulses for each subframe (SF) according to the total number of pulses, and supplies them to the driver controller
14
. The period of a display frame is specified by the vertical synchronizing signal (Vsync) supplied from the outside and the signal vsync is supplied to the gain control circuit
11
, the data converter
14
, and the power control circuit
15
, and is also supplied to the driver controller
14
via the power control circuit
15
.
The driver controller
14
generates and puts out drive signals that control the X driver
2
, the Y driver
3
, the address driver
4
, the data converter, and so forth, based on the abovementioned number of radiation pulses for each SF, Vsync, and clocks from a clock source (not shown). According to the drive signals supplied from the driver controller
14
, each part generates a drive signal (waveform) to be applied to the panel
1
.
FIG. 2
shows drive signals of a subframe in a PDP display apparatus of a so-called write address type, in which the address period and the sustaining discharge period are separated. The subframe will be explained later. The operations of a PDP display apparatus are explained with reference to FIG.
2
. In this example, a subframe is divided into the reset period, the address period, and the sustaining discharge period. In the reset period, all cells are set to the same status. In the address period, scan pulses are applied to the Y electrodes sequentially, and address pulses are synchronously applied to the address electrodes according to the display data (address data). While scan pulses are applied to the Y electrode of a line, address pulses are applied to the address electrode of a cell that is caused to emit light among the cells of the line, and address pulses are not applied to the address electrode that is not caused to emit light. In the cell to which address pulses are applied, address discharge is caused to occur and wall-charge is accumulated on the surface of the electrode of the cell. This process is applied to all lines in succession. As a result, all cells are set to a status in accordance with the display data of the subframe, and wall-charge accumulates. In the sustaining discharge period, sustaining pulses are applied to the Y electrodes and the X electrodes alternately, and discharge is caused to occur in a cell in which wall-charge has accumulated and the cell emits light. In this case, the luminance is determined by the length of the sustaining discharge period, in other words, the number the sustaining pulses (number of times discharge for light emission is performed).
The gray scale representation in a PDP is realized by dividing a display frame into plural subframes and by combining the lit subframes. The luminance of each subframe is determined based on the number of the sustaining pulses. Though the luminance ratio of each subframe may be set at a special ratio in order to suppress the problem of color false contour, in a subframe structure as shown in
FIG. 3
, each term of the luminance ratio is a value of 2 to the nth power and the number of gray levels for a certain number of subframes is the maximum, therefore, this structure is widely used. In
FIG. 3
, the ratio of the number of sustaining discharge pulses of six subframes SF
0
through SF
5
is 1:2:4:8:16:32, and 64 gray levels can be represented by combining them, and each bit of the 6-bit display data corresponds to SF
0
through SF
5
in this order. For example, when the gray level of a display data of a cell is the 25
th
(
1
A in the hexadecimal system), SF
1
, SF
3
, and SF
4
are lit and other SF
0
, SF
2
, and SF
5
are not lit. Here, the total number of sustaining pulses of all the subframes of a display frame is referred to as the total number of radiation pulses n. That is, the total number of radiation pulses is the number of sustaining pluses when all the subframes are lit, and is also the number of pulses that can be lit to the maximum extent for a cell during a display frame, for ex
Ooe Takayuki
Toda Kosaku
Ueda Toshio
Anyaso Uchendu O.
Fujitsu Hitachi Plasma Display Limited
Saras Steven
Staas & Halsey , LLP
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