Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-25
2003-02-18
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S185220
Reexamination Certificate
active
06522585
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to non-volatile memories, and, more specifically, to methods for treating over-erased memory cells in electrically erasable and programmable read only memories (EEPROMs).
2. Background Information
A non-volatile memory (NVM) cell stores information by altering the control-gate voltage required to enable source-drain current conduction. This is known as the cell's threshold voltage, V
t
. Programming is the operation used to raise this conduction threshold, while erase is an operation used to lower the cell's threshold. A virtual-ground architecture is one of a few schemes used to assemble NVM cells into arrays. A virtual-ground array offers relatively high area efficiency by allowing the adjacent cell to share access bit-lines.
A schematic of a virtual-ground array
100
is illustrated in
FIG. 1
a
, with the various parts of an individual cell
120
also described in
FIG. 1
b
. Here, vertical bit-lines connect NVM cell source and drain terminals,
123
and
124
, while horizontal word-lines connect to the terminals of the control gate
121
. The program status of a specific cell within the array is isolated for reading by applying the appropriate bit-line and word-line bias voltages. In
FIG. 1
, cell &agr;
2
102
is read when word-line WL
0
130
and bit-line BL
&agr;1
111
are biased high while bit-line BL
&agr;2
112
and word-line WL
1
131
are set low. Alternatively, cell &agr;
1
is read when BL
&agr;0
110
is set low instead of BL
&agr;2
112
. This array architecture derives its name from this use of ground bias in selecting individual cells instead of having dedicated source bit-lines. Further details on the virtual-ground architecture are given in J. Pasternak, et. al., “4 Mb Alternate Metal, Virtual Ground FLASH Memory,” 1998 NVSM Workshop, Monterey, Calif. (USA), which is hereby incorporated by this reference, and also in the other reference incorporated below.
An important consideration for virtual-ground operation is the influence of neighboring cells on the selected cell. Neighbor cells can draw current away from the cell being accessed; an unwanted situation since it interferes with the accuracy and efficiency of both read and program operations. This neighbor effect is typically reduced by biasing neighboring bit-lines to the same levels as those accessing the cell, as illustrated in FIG.
2
. Here, a current
201
is flowing in cell &agr;
2
, for example during reading or programming, by setting the drain, connected to BL
&agr;1
211
, and control gate, connected to word-line WL
0
230
, both high, while the source, connected to bit line BL
&agr;2
212
, and other word-lines are low. A current in the neighboring cells &agr;
1
and &agr;
3
, respectively due to the drain-neighbor leakage
202
or source-neighbor leakage
203
, may also be induced unless these cells are biased properly with a high drain neighboring bit-line BL
&agr;0
210
and the low source neighboring bit-line BL
&agr;3
213
.
By definition, FLASH-cell erasure requires the erase of at least an entire sector, which is usually a word-line, of cells. Due to differences in erase rates of the various cells on this common word-line, cells may often erase beyond the maximum lower threshold voltage needed to reliably indicate an erased state. As a result, neighbor effects are significantly enhanced for these over-erased cells. Soft programming is a technique used to gently raise the thresholds of over-erased cells prior to the actual data programming.
Prior art methods for treating over-erased cells include individually programming the over-erased cells until they are in the erased, or “ground” state. More details on some of these techniques can be found in U.S. Pat. Nos. 5,172,338 and 5,272,669, both of which are assigned to SanDisk Corporation and both of which are hereby incorporated herein by this reference.
Source-side injection is one of the many mechanisms that can be used to program an NVM cell.
FIG. 3
a
shows a device cross-section of a structure for programming by source-side injection, with its schematic symbol shown in
FIG. 3
b
. The cell
300
shown in these figures has a source
303
and drain
305
that define the channel region between them, over which is the control gate
309
and the floating gate
307
as well as the side-wall
301
. This structure generally requires a low-conductive channel region
311
near the source side of the device, and a highly conductive, floating-gate channel region
313
. In this device, the lateral field along the channel is enhanced at the floating gate's source side through the combination of the side-wall and floating-gate channel regions. The sidewall device
301
is biased through coupling from the relatively high control gate voltage needed for programming. More detail on source-side injection is given, for example, in A. T. Wu, T. Y. Chan, P. K. Ko, C. Hu, “A Novel High-Speed, 5-Volt Programming EPROM Structure with Source-Side Injection,” 1986 IEDM Technical Digest, pp. 584-587, which is hereby incorporated herein by this reference.
In order to limit the total soft-program current and also control the soft-program rate, the cell's programming current can be controlled from the source-side when using source-side injection. A complication to this approach for virtual-ground arrays is the source-neighbor effect due to over-erased cells.
FIG. 4
shows a program current applied to cell &agr;
2
using a source-limit circuit in a virtual ground array of cells like those of
FIG. 3
a
in the situation where neighboring cell &agr;
3
is over-erased. To program cell &agr;
2
, the current
401
is set up by setting bit-line BL
&agr;1
411
and word-line WL
0
420
high. The other word-lines, such as WL
1
421
, are set low. The program current
401
is then controlled by the current limiter
431
on the source bit-line BL
&agr;2
412
. Although the bit-line BL
&agr;2
412
is connected to ground below
431
, the voltage level at node A is some non-zero value that is dependent on the characteristics of the cell &agr;
2
and is very dynamic. Since the source neighbor bit-line BL
&agr;3
413
is at ground and the word-line WL
0
420
is high, instead of the programming current flowing solely through the current-limit circuit
431
, an uncontrolled source-neighbor leakage current
403
runs through cell &agr;
3
and out through source-neighbor bit line BL
&agr;3
413
.
This resultant uncontrolled current through cell &agr;
3
results in a number of problems. A first problem is power consumption. This &agr;
3
sort of leakage is an uncontrolled flow of current. As a large number of cells are generally programmed in parallel, this results in greatly increased power consumption, which is a particular problem in low power applications. A second problem is that since the amount of current
403
flowing in cell &agr;
3
cannot be controlled, the current
401
in the cell to be programmed can not be controlled accurately. The more current flowing through &agr;
2
, the faster it will program. Thus, by not being able to control the current accurately, a greater variation in the program rates of the cells being programmed results. Additionally, if the cell &agr;
2
is over-erased, it will draw more current, further compounding the programming rate problem.
Therefore, a solution to this problem of improving the control of the soft-programming current in a virtual ground arrays is needed.
SUMMARY OF THE INVENTION
The present invention is directed to controlling programming current in a virtual-ground array memory architecture. The invention consists of circuitry to bias the array such that no source neighbors occur during soft programming. A feature of this bias configuration is that two cells are simultaneously soft-programmed. This dual-cell operation relies on the fact that neighbor cells will have similar electrical characteristics and will therefore program at a similar rate.
In one exemplary embodiment, the cells of the non-volatile memory array are
Hoang Huan
SanDisk Corporation
Skjerven Morrill LLP
LandOfFree
Dual-cell soft programming for virtual-ground memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual-cell soft programming for virtual-ground memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-cell soft programming for virtual-ground memory arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3139891