Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
2002-05-13
2003-02-11
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
C327S564000
Reexamination Certificate
active
06518835
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and, more particularly, the invention relates to improvements in a power supply circuit for a dynamic RAM (random access memory), including peripheral circuits and bonding pads disposed in a central portion of a semiconductor chip, and power supply circuits for stepping down a source voltage supplied from an external terminal and for supplying stepped-down voltages to the peripheral circuits and the like.
U.S. Pat. No. 5,602,771 discloses an example of a dynamic RAM in which bonding pads and corresponding peripheral circuits are disposed in a central portion of a semiconductor chip and a source voltage supplied from an external terminal is stepped down and supplied to internal circuits including the peripheral circuits. In the dynamic RAM of U.S. Pat. No. 5,602,771, an area in which the peripheral circuits are arranged is disposed in a cross-like shape in the longitudinal and lateral central portions of the memory chip, and memory arrays are respectively disposed in four areas divided by the cross-shaped area. In addition, X- and Y-decoder address signal generating circuits, internal step-down power supply circuits and the like are disposed in the cross-shaped central portion, i.e., the central portion of the memory chip.
SUMMARY OF THE INVENTION
If the peripheral circuits are disposed in the longitudinal and lateral central portions of the memory chip in the above-described manner, interconnect channels are formed along the respective circuit arrays. Prior to the present invention, the present inventors considered a construction in which redundant circuits and the like were disposed in the central portion of a memory chip, which extended in a direction parallel to the shorter sides thereof, and an interconnect channel using a second-layer metal interconnect layer was formed as a signal path for the redundant circuits, while peripheral circuits, such as address buffers and data input/output circuits, were disposed in the central portion of the memory chip, which extends in a direction parallel to the longer sides thereof, and an interconnect channel using a third-layer metal interconnect layer was formed as a signal path for the peripheral circuits.
By adopting this construction, it is possible to realize a rational circuit layout by using a first-layer metal interconnect layer to form logic circuits and the like, which constitute constituent units of individual circuits, and by using an interconnect channel overlying the first-layer metal interconnect layer as an interconnect line which interconnects the logic circuits. However, if this construction is adopted, a portion where the two interconnect channels intersect each other is formed in the central portion of the memory chip, so that the circuits must be formed by using only the first-layer metal interconnect layer.
The first-layer metal interconnect layer uses a high-melting point metal material containing tungsten (W) so that the first-layer metal interconnect layer can be made resistant to a heating process which is employed after the layer has been formed, and so, in an interconnect line using such a first-layer metal interconnect layer, the resistance becomes comparatively large. For example, there is a case where the resistivity of the first-layer interconnect line becomes larger than the resistivity of the second-layer interconnect line. Accordingly, even if a circuit is constructed with a skillful interconnect layout by using the first-layer metal interconnect layer, it is difficult to obtain a circuit having high performance because of the comparatively large resistance of the interconnect line. For this reason, the present inventors have developed a semiconductor integrated circuit device which realizes a rational circuit layout which makes efficient use of the portion where the aforesaid two interconnect channels intersect each other.
An object of the present invention is to provide a semiconductor integrated circuit device in which a rational layout of circuit elements is realized without lowering the performance of the entire circuit. The above and other objects and novel features of the present invention will become more apparent from the following description of the present invention, taken in conjunction with the accompanying drawings.
A representative feature of the invention disclosed in the present application will be described below. In a semiconductor integrated circuit device comprising a first interconnect channel including a plurality of second layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage and which is provided with stabilizing capacitors, wherein a large part of the stabilizing capacitors are occupied by capacitors formed in an area in which the second- and third-layer metal interconnect layers intersect each other.
REFERENCES:
patent: 5966518 (1999-10-01), Usui
Egawa Hidekazu
Fujii Isamu
Nakai Kiyoshi
Riho Yoshiro
Suzuki Yukihide
Antonelli Terry Stout & Kraus LLP
Wells Kenneth B.
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