Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2002-09-10
2003-10-14
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S777000
Reexamination Certificate
active
06633079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to RF MEMS (MicroElectroMechanical Systems) technology and more particularly to MEMS with wafer level interconnection to electronics on low-resistivity substrate material.
2. Background of Invention
RF MEMS technology has been targeted for insertion in a wide range of military applications from multi-band multi-mode communication systems to inertial navigation systems to sensors. In fact, RF MEMS technology insertion plays a major role in numerous current DARPA funded programs such as Ultra Comm and the Airborne Communications Node (ACN).
This technology could be applied to these programs plus new military insertion opportunities such as targeting systems, satellite communications, high speed tactical data link systems, electronic warfare and countermeasure systems, signal intelligence systems, and antenna systems.
This technology could also be applied to consumer electronics applications such as telecommunications (cellular telephone, back-haul, etc.) commercial aircraft, commercial radar, etc. where the distinct performance advantages and small form factor provided by the combination of RF MEMS and silicon germanium (SiGe) or other electronic circuits are desired.
This technology could also be applied to consumer electronics applications such as telecommunications (cellular telephone, back-haul, etc.) commercial aircraft, commercial radar, etc. where the distinct performance advantages and small form factor provided by the combination of RF MEMS and silicon germanium (SiGe) or other electronic circuits are desired.
Many hetero-junction technologies, epitaxial methods, and substrate materials have been considered incompatible. Specifically, RF MEMS fabrication technology has been considered incompatible with silicon germanium (SiGe) fabrication technology. RF MEMS technology requires a high resistivity substrate material to maximize the circuit RF performance. Typically SiGe circuits are processed on low resistivity material.
Raytheon has investigated the integration of RF MEMS circuitry on a low resistivity SiGe substrate using a “direct integration” (DI) approach. The primary technical challenge associated with direct integration RF MEMS circuitry with sophisticated electronics is overcoming the influence of the low-resistivity substrate material, typically used by SiGe manufacturers, on the insertion loss of the RF MEMS circuit.
Direct integration (DI) was investigated by Raytheon for overcoming the detrimental affects of the low-resistivity substrate on microwave circuitry. DI involves building a second dielectric layer on top of the substrate to serve exclusively as the microwave substrate. DI, however, has a number of technical challenges.
RF MEMS circuits produced by Raytheon require a smooth substrate. This is necessary due to the geometry of the structures being produced. The flatness of the dielectric material for the DI approach is currently unknown. Secondly, the RF performance of the circuit can be limited by the thin microwave dielectric layer.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention wafer level interconnect removes the requirements for substrate material as an issue. Each technology processes their circuitry on the required base material and minimizes the need for additional process development. Following initial processing, the two wafers are electrically interconnected with vertical electrical interconnections.
The wafer level interconnect invention will enable the integration of these two (and other) technologies where previously integration through wafer fabrication has been limited by a requirement for differing base substrate materials. This invention may also provide benefits for wafer level packaging of integrated circuits on silicon substrates where the electrical signal must be isolated from the substrate.
In accordance with one embodiment of the invention, a method for coupling a first and a second substrate is provided that includes coupling the first substrate that includes a high resistivity material to a first circuitry and coupling the second substrate that includes a low resistivity material to a second circuitry. A dielectric lid is positioned between the first and second circuitries, the dielectric lid being operable to provide a gap between the first and second substrates. The first and second substrates are coupled with a plurality of interconnecting conductors that each extend to the first and second substrates such that an electrical coupling is provided between the first and second circuitries.
REFERENCES:
patent: 4825284 (1989-04-01), Soga et al.
patent: 4935386 (1990-06-01), Nakagawa et al.
patent: 5164328 (1992-11-01), Dunn et al.
patent: 5417235 (1995-05-01), Wise et al.
patent: 5949135 (1999-09-01), Washida et al.
patent: 6049702 (2000-04-01), Tham et al.
patent: 6093969 (2000-07-01), Lin
patent: 6097096 (2000-08-01), Gardner et al.
patent: 6307452 (2001-10-01), Sun
patent: 6489670 (2002-12-01), Peterson et al.
patent: 10027234 (2000-12-01), None
patent: 2 780 200 (1999-12-01), None
patent: WO97/12397 (1997-04-01), None
Ables Billy D.
Cheever James L.
Ehmke John C.
Goldsmith Charles L.
Baker & Botts L.L.P.
Raytheon Company
Wilson Allan R.
LandOfFree
Wafer level interconnection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wafer level interconnection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level interconnection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3137573