Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-05-01
2003-10-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S230080
Reexamination Certificate
active
06636455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that takes in an external control signal, an external address signal, and an external data signal in synchronization with a clock signal.
2. Description of the Background Art
In recent years, a DDR (double data rate) SDRAM (synchronous dynamic random access memory) is developed which takes in an external data signal in synchronization with both a rising edge and a falling edge of a clock signal. In this DDR SDRAM, a data strobe signal is used to minimize the time skew between chips in a memory system, and a writing operation having a writing latency of one clock cycle is carried out.
However, since such a DDR SDRAM has a writing latency, the minimum period of time tRC needed for one data writing corresponds to five clock cycles (See FIG.
12
), so that the testing time is long if the test is carried out at a low frequency, thereby raising a problem of high costs for testing.
SUMMARY OF THE INVENTION
Thus, a principal object of the present invention is to provide a semiconductor memory device having a short testing time.
A semiconductor memory device according to the present invention includes a memory array having a plurality of memory cells arranged in a matrix form, a word line disposed in correspondence with each row, and a bit line pair disposed in correspondence with each column; a row selection circuit that selects the word line of the row corresponding to the row address signal in response to an active command and activates each memory cell in the row; a column selection circuit that selects the bit line pair of the column corresponding to the column address signal in response to a writing command; and a writing circuit that, in a normal operation mode, takes in the external data signal when a predetermined first period of time passes after the writing command is issued, and, in a testing mode, takes in the external data signal in response to the active command being issued, to write the external data signal into the memory cell activated by the row selection circuit via the bit line pair selected by the column selection circuit. Therefore, this semiconductor memory device, in the testing mode, performs a writing operation without having a writing latency, so that the testing time is short even if the test is carried out at a low frequency.
Preferably, the semiconductor memory device has two memory arrays, receives two external data signals consecutively input in synchronization with a leading edge and a trailing edge contained in the external clock signal, and receives an external data strobe signal having a leading edge and a trailing edge that are synchronized with the two external data signals. The row selection circuit selects a word line for each memory array, and the column selection circuit selects a bit line pair for each memory array. The writing circuit takes in the two external data signals in response to the leading edge and the trailing edge of the external data output signal, writes one of the two external data signals into the memory cells of one of the two memory arrays, and writes the other external data signal into the memory cells of the other memory array. In this case, since the external data signal are taken in in synchronization with both the leading edge and the trailing edge of the external clock signal, the writing operation can be carried out at a higher speed.
Preferably, the writing circuit includes an input buffer that, in the normal operation mode, is activated in response to the active command being issued and, in the testing mode, is activated at all times, to generate an internal data signal in accordance with the external data signal; first and second latch circuits that are respectively disposed in correspondence with the two memory arrays; and a first switching circuit that gives the internal data signal generated in the input buffer to the first latch circuit in response to the leading edge of the external data strobe signal, and gives the internal data signal generated in the input buffer to the second latch circuit in response to the trailing edge of the external data strobe signal. In this case, since the input buffer is activated at all times in the testing mode, the external data signal can be input before the active command. Further, the first and second latch circuits and the first switching circuit can convert the two serial internal data signals into two parallel internal data signals.
Preferably, the semiconductor memory device further includes a precharging circuit that precharges each bit line pair to a predetermined potential in response to a precharging command; and a first signal generating circuit that, in the normal operation mode, takes in a memory array selection signal contained in the external address signal in response to the writing command being issued and, in the testing mode, takes in the memory array selection signal in response to the precharging command being issued, to output first and second signals in accordance with the memory array selection signal. The writing circuit further includes third and fourth latch circuits that are respectively disposed in correspondence with the two memory arrays; and a second switching circuit that gives the internal data signals output from the first and second latch circuits respectively to the third and fourth latch circuits when the first signal is output from the first signal generating circuit, and gives the internal data signals output from the first and second latch circuits respectively to the fourth and third latch circuits when the second signal is output from the first signal generating circuit. In this case, since the memory array selection signal is taken in in response to the precharging command that is input before the active command and the writing command in the testing mode, the writing operation without having a writing latency can be carried out easily.
Preferably, the semiconductor memory device further includes a precharging circuit that precharges each bit line pair to a predetermined potential in response to a precharging command; and a first signal generating circuit that, in the normal operation mode, receives a memory array selection signal contained in the external address signal in response to the writing command being issued, to output a first or second signal in accordance with the memory array selection signal and, in the testing mode, outputs a preselected one of the first and second signals. The writing circuit further includes third and fourth latch circuits that are respectively disposed in correspondence with the two memory arrays; and a second switching circuit that gives the internal data signals output from the first and second latch circuits respectively to the third and fourth latch circuits when the first signal is output from the first signal generating circuit, and gives the internal data signals output from the first and second latch circuits respectively to the fourth and third latch circuits when the second signal is output from the first signal generating circuit. In this case, since there is no need to take in the memory array selection signal in the testing mode, the writing operation without having a writing latency can be carried out more easily.
Preferably, the semiconductor memory device further includes a second signal generating circuit that, in the normal operation mode, outputs a third signal when a predetermined second period of time passes after the writing command is issued and, in the testing mode, outputs the third signal in response to the writing command. The writing circuit further includes a third switching circuit for giving the internal data signals output from the third and fourth latch circuits respectively to the selected memory cells of the two memory arrays in response to the third signal being output from the second signal generating circuit. In this case, the writing operation having a writing latency can be carried out i
Maruyama Yukiko
Sawada Seiji
Auduong Gene N.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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