Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-02-08
2003-12-30
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185190
Reexamination Certificate
active
06671207
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of programming multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory.
Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM. A Flash device is a non-volatile memory comprising an array of cells that can store a pre-determined number of logic “0”'s and “1”'s. The stored “1”s and “0”s maintain their state in the absence of external power. These bits can be modified millions of times over the life-time of the device.
An example of a typical configuration for an integrated circuit including a multi-level cell flash memory array
100
and circuitry enabling programming, erasing, and reading for memory cells in the array
100
is shown in FIG.
1
. The flash memory array
100
includes individual cells
102
. Each cell
102
has a drain connected to a bitline
104
, each bitline being connected to a bitline pull up circuit
106
and column decoder
108
. The sources of the array cells are connected to Vss, while their gates are each connected by a wordline
109
to a row decoder
110
.
The row decoder
110
receives voltage signals from a power supply
112
and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine
114
. Likewise, the bitline pull up circuit
106
receives voltage signals from the power supply
112
and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor
114
. Voltages provided by the power supply
112
are provided as controlled by signals received from processor
114
.
The column decoder
108
provides signals from particular bitlines
104
to sense amplifiers or comparators
116
as controlled by a column address signal received from processor
114
. The sense amplifiers
116
further receive voltage reference signals from reference
118
. The outputs from sense amplifiers
116
are then provided through data latches or buffers
120
to processor
114
.
As mentioned above, the memory array
100
includes multi-level storage cells
102
. Multi-level storage refers to the ability of a single memory cell
102
to represent more than a single binary bit of data. A conventional memory cell depicts two states or levels, usually referred to as logic “0” and logic “1”. A multi-level cell could represent as many as 256 states, or a byte of information.
Multi-level cell storage is obtainable in flash design because a flash memory cell can be programmed to provide multiple threshold voltage (vt) levels. The different vt levels can be sustained over time in a flash memory cell
102
, even after repeated accesses to read data from the cell. For example, 16 vt levels stored in a flash memory cell can represent data in four conventional memory cells. Thus, an array of multi-level flash memory cells
102
which can store up to 16 vt levels can provide 4 times the storage capacity of conventional memory cells which only store a binary bit per cell. An example of a multi-level memory array is discussed in U.S. Pat. No. 5,973,958, the entire contents of which are incorporated herein by reference.
Programming of the flash memory array
100
is executed on a word-line basis. The word-line
109
is considered the row address. The word-line will cross multiple bit-lines
104
. The bit-line
104
is considered the column address. Each bit-line
104
contains buffer logic to interface to the selected core cell during program, read and erase operations.
FIG. 2
illustrates a selected and unselected bit-line during programming. The unselected bit (bit not to be programmed) is considered inhibited. The bit-line is inhibited from the effects of the program pulse. The selected bit (bit to be programmed) is referred to as uninhibited. This bit will be programmed during the program pulse.
To program a multi-level cell in the flash memory array
100
, high gate-to-drain voltage pulses are provided to the cell from power supply
112
while a source of the cell is grounded. For instance, during programming typical gate voltage pulses of 18V are each applied to a cell, while a drain voltage of the cell is set to 3.3V and its source is grounded.
As shown in
FIG. 2
, the program voltage PVpp of 18V will be applied to the selected word-line (column address). A substantially lesser voltage, such as 10V, will be applied to unselected word-lines. An uninhibited word-line will have a strong field generated across the device. In particular,
FIG. 2
shows that with Vss of 0V being applied to one end of a bit-line
109
to be uninhibited, the source/drain regions of the bit-line will couple to 0V or ground. This will make the applied field appear much stronger so that effective programming can occur. A high field generated across the memory device will cause electron injection into the floating gate of the selected cell exponentially proportional to strength of the field. This programming procedure results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
Each programmed cell requires a specific amount of applied electric field to obtain the desired programmed vt level. The amount of electric field determines the program speed of a bit-cell. Fast cells will need less applied field while slow cells will need more. The electric field is applied through several program pulses. The use of program pulses allows the device to control program distributions. After each pulse, the cells are program-verified to see if the target vt has been achieved. Using multiple program pulses allows the device to stop programming fast bits while completing the programming the slow bits.
Program-verify allows the device to stop programming specific bit-cells when a desired level has been obtained. All memory cells start in the Erase State (E) as seen in FIG.
3
. Depending on data, specific bits will be programmed to the higher 3 states. Once programmed, these bits can be read by the external system.
To program each memory cell, it can take several program pulses. After each program pulse, a program-verify evaluation occurs. As in
FIG. 4
, the program-verify guarantees that each cell is at a minimum (PgVfyA) vt state. Program-verify is needed because of variation in program speeds among the bit-cell population. Fast bits may achieve the desired vt level in 5 program pulses. Slow bit-cells may require 10 program pulses to complete. Program verify allows specific bits to be disabled from further programming when the desired vt level is achieved.
FIG. 4
indicates the difference between the read and program-verify levels. The difference between the read and program-verify level is chosen to supply a margin to compensate for reliability and functional variations. (i.e., VCC, temperature) A program-verify occurs after each program pulse to determine if the selected bit is at the desired vt level.
Conventional program flows have
Advanced Micro Devices , Inc.
Auduong Gene N.
Ho Hoai
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