Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-08-29
2003-02-04
Bella, Matthew C. (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S559000
Reexamination Certificate
active
06515648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a driving circuit of a display device. Besides, the present invention relates to a display device using the driving circuit.
2. Description of the Related Art
Techniques of manufacturing a semiconductor device, for example, a thin film transistor (TFT), which has a semiconductor thin film formed on an inexpensive glass substrate, have been making rapid progress in recent years. This is because there is an increasing demand for active matrix liquid crystal display devices (hereafter referred to as liquid crystal display devices).
In the liquid crystal display device, several hundred thousands to several millions of TFTs are arranged in matrix in a pixel portion, and electric charges going into and out of pixel electrodes that are connected to each TFT are controlled by the switching function of the TFTs.
Conventionally, thin film transistors using an amorphous silicon film formed on a glass substrate are arranged in the pixel portion.
Further, in recent years, a technique is known in which quartz is utilized as a substrate and thin film transistors are manufactured using a polycrystalline silicon film. In this case, both a driver circuit and a pixel portion are integrally formed on the quartz substrate.
Still further, recently, a technique in which thin film transistors using a crystalline silicon film are formed on a glass substrate by laser annealing or the like is also known.
Liquid crystal display devices are mainly used in notebook personal computers. Different from analog data used in the current television signals (NTSC or PAL) or the like, the personal computer outputs digital data to a display device. Conventionally, digital data from a personal computer are converted into analog data and then inputted into the liquid crystal display device, or to a liquid crystal display device that utilizes an externally attached digital driver.
Therefore, a liquid crystal display device having a digital interface capable of directly inputting digital data from outside is in the spotlight.
Here,
FIG. 17
shows a part of a source driver of a liquid crystal display device including a digital interface to which attention has been paid recently. In
FIG. 17
, reference numeral
8000
designates a shift register circuit which includes a plurality of register circuits
8010
. The register circuit is constituted by four clocked inverter circuits and a NAND circuit. Reference numeral
8100
designates a sampling circuit which includes a plurality of analog switches
8110
.
Note that a scan direction switching circuit is included in the shift register circuit
8000
shown in FIG.
17
. The scan direction switching circuit is a circuit for controlling the order of the output of the timing pulse from the shift register circuit
8000
from left to right or from right to left in accordance with a scan direction switching signal inputted from outside.
The shift register circuit
8000
generates a timing pulse on the basis of a clock signal (CLK), a clock inversion signal (CLKB), and a start pulse supplied from the outside, and sends the timing pulse to the sampling circuit. The sampling circuit
8100
samples (takes in) analog video data (VIDEO) inputted from the outside on the basis of the timing pulse from the shift register circuit
8000
, and outputs to a source signal line.
In the conventional shift register circuit
8000
as shown in
FIG. 17
, one register circuit
8010
is constituted by four clocked inverter circuits and a NAND circuit, the shift register circuit
8000
is complicated, and the number of elements constituting it is large. Under the present circumstances in which a liquid crystal display device of higher resolution is demanded, with the improvement of the resolution, the area of the shift register circuit becomes large, and the number of elements constituting the shift register circuit is also increased.
Because of this increase in the number of elements, the production yield in the entire liquid crystal display device may become worse. Further, if the possessed surface area of the circuits becomes larger, it hinders the making of small scale liquid crystal display devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is therefore to attain improvement in production yield and compactness of the liquid crystal display device by providing a driver circuit that is simple as well as possessing a small area of the substrate.
Reference will be made to FIG.
1
.
FIG. 1
shows a shift register circuit
100
of the present invention. The shift register circuit of the present invention includes a plurality of register circuits (a first register circuit
110
, a second register circuit
120
, a third register circuit
130
, a fourth register circuit
140
, and a fifth register circuit
150
). For convenience of explanation,
FIG. 1
shows the five-stage shift register circuit
100
including the first to fifth register circuits. However, the shift register circuit of the present invention can be made an n-stage shift register circuit including first to n-th (n) register circuits (n is a natural number).
A description will be made on the first register circuit
110
as an example. The first register circuit
110
includes a clocked inverter circuit
111
and an inverter circuit
112
. Both are connected in series with each other so that an output signal of the clocked inverter circuit
111
becomes an input signal of the inverter circuit
112
. Further, the first register circuit
110
includes a signal line
113
by which an output signal of the inverter circuit
112
is transmitted, and parasitic capacitance generated by this signal line
113
and a power source line or a ground line may be considered as an element constituting the register circuit.
Since the signal line
113
is connected to many elements, e.g. an analog switch, a signal line of the pixel portion, an adjacent register circuit, etc., and parasitic capacitance is large, it has a high load. The shift register circuit of the present invention uses the fact that the parasitic capacitance of the signal line
113
is large so that it has a high load.
Note that the second register circuit
120
, the third register circuit
130
, the fourth register circuit
140
, and the fifth register circuit
150
have also the same structure as the first register circuit
110
. That is, the second register circuit
120
includes a clocked inverter circuit
121
, an inverter circuit
122
, and a signal line
123
. The third register circuit
130
includes a clocked inverter circuit
131
, an inverter circuit
132
, and a signal line
133
. The fourth register circuit
140
includes a clocked inverter circuit
141
, an inverter circuit
142
, and a signal line
143
. The fifth register circuit
150
includes a clocked inverter circuit
151
, an inverter circuit
152
, and a signal line
153
.
Besides, a clock signal (CLK), a clock back signal (CLKB) with a reverse phase to the clock signal, and a start pulse (SP) are inputted to the shift register circuit
100
from the outside. These signals are inputted to all register circuits (the first register circuit
110
, the second register circuit
120
, the third register circuit
130
, the fourth register circuit
140
, and the fifth register circuit
150
) constituting the shift register circuit of the present invention.
Here, the operation of the shift register circuit of the present invention will be described.
The clocked inverter circuit
111
of the first register circuit
110
operates in synchronization with the inputted clock signal (CLK) and the clock back signal (CLKB), inverts the logic of the inputted start pulse (SP), and outputs to the inverter circuit
112
. The inverter circuit
112
inverts the logic of the inputted pulse, and outputs to the signal line
113
and the next stage second register circuit
120
.
A pulse outputted from the former stage first register circuit
110
is inputted to
Hayashi Keisuke
Tanaka Yukio
Bella Matthew C.
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Nguyen Hau
Semiconductor Energy Laboratory Co,. Ltd.
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