Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-09-18
2003-10-28
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S254000, C438S692000, C257S306000, C257S309000
Reexamination Certificate
active
06638830
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a high-density capacitor, and more particularly, to a method for fabricating a high-density capacitor having a vertical three-dimensional (3-D) structure.
2. Description of the Prior Art
In the present semiconductor mix mode integrated circuit process, most often the conventional plate capacitor is applied to connect with a metal oxide semiconductor (MOS) transistor to form a memory device. The conventional plate capacitor has a three-layer plate stacked structure composed of a bottom electrode plate, a capacitor dielectric layer, and a top electrode plate, and is formed by utilizing different photo masks three times to define patterns of each layer. However, the plate stacked structure needs a large chip area to achieve demands of the capacitor. Therefore, reducing the demand space that defines the capacitor structure on the chip (i.e. increase the capacitor density), raising the device integration, decreasing numbers of the photo masks, and lowering the production costs, have become the most important points of fabricating the capacitor structure.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method for fabricating a high-density capacitor to increase the capacitor density and raise the device integration.
It is another object of the claimed invention to provide a high-density capacitor to decrease numbers of the photo masks and lower the production costs.
According to the preferred embodiment of the claimed invention, the high-density capacitor is formed in a semiconductor substrate that comprises a dielectric layer. First, at least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench is formed in the dielectric layer, and the second trench having a joint side wall with the first trench. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional (3-D) structure.
In the claimed invention, the high-density capacitor uses the 3-D structure so as to reduce the chip area substantially, increase the capacitor density, and increase the device integration. In addition, the first conductive layer and the second conductive layer are both lodged into the dielectric layer positioned on the semiconductor substrate, so that the capacitor process of the claimed invention can be integrated with other interconnection processes. Only one photo mask is utilized to form the trench structures of the capacitor and the interconnection so as to simplify the processes, decrease numbers of the photo masks, and reduce the production costs.
REFERENCES:
patent: 6165804 (2000-12-01), Fazan et al.
patent: 6168988 (2001-01-01), Schindler et al.
patent: 6518120 (2003-02-01), Park
Cheng Yi-Fang
Hsu Chia-Lin
Tsai Teng-Chun
Cao Phat X.
Doan Theresa T.
Hsu Winston
United Microelectronics Corp.
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