Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-01-31
2003-11-11
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000, C438S048000, C438S239000, C438S244000, C438S253000, C438S689000, C438S706000, C257S068000, C257S071000, C257S298000, C257S301000, C257S303000, C257S414000, C257S421000, C365S212000, C365S213000
Reexamination Certificate
active
06645822
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells, in particular Magneto-Resistive Random Access Memory (“MRAM”) cells or the like, in which at least one circuit element is situated in a crossing area of at least two conductor elements and is situated therebetween.
In many semiconductor circuit systems, circuit elements are provided at crossing areas of two conductor elements (e.g., metallic printed conductors or the like), e.g., also between the conductor elements. Such a configuration is true, for example, for a multiplicity of memory devices or the like, and, in particular, for memory cells based on what are referred to as MRAM cells. In what are referred to as crosspoint MRAM cells, between each two crossed metallic conductors, the memory elements are provided in the form of what are called tunnel magneto-resistive or tunnel magneto-resistance (“TMR”) layer stacks, having very small dimensions.
In the manufacturing of semiconductor circuit systems, these systems are often built up successively in layers. There is a difficulty that, in particular, in situating circuit elements in crossing areas of conductor elements, due to the frequently very small dimensions, a high degree of geometric precision and reproducibility can be achieved only at a relatively great expense. The geometric precision and reproducibility is, however, necessary to ensure, e.g., in MRAM cells, a corresponding reproducibility also of the magnetic properties of the memory cells.
In prior art methods, the circuit elements, and, thus, in particular, the TMR stacked layers, are processed by separate lithography steps and lithography planes. As such, after the application of a first class of conductor elements or printed conductors B likewise in the context of a separate lithography layer with a separate lithography step B, the circuit elements, e.g. the MRAM cells, are then subsequently formed in a separate segment of the process. Subsequently, the conductor elements or printed conductors of the second class are then likewise structured in a separate lithography step.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for manufacturing a semiconductor circuit system that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that enables structuring of circuit elements with a high degree of geometrical precision in a particularly simple and, at the same time, reliable manner.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for manufacturing a semiconductor circuit system having a plurality of memory cells in which at least one circuit element is disposed substantially in a crossing area of at least two conductor elements and between the conductor elements, including the steps of forming at least one substrate region with a surface region having an upper side, forming at least one first conductor element and at least one second conductor element substantially on the surface region, the first conductor element and the second conductor element having at least one crossing area, the first conductor element having a first side facing away from the substrate region, and the second conductor element having a second side facing the substrate region, forming at least one circuit element substantially in the crossing area and between the first side and the second side, structuring the circuit element at least partially simultaneously with a structuring of at least one of the first and second conductor elements in a first etching step for the first conductor elements and a respective first part of the circuit element, executing the first etching step in substeps including a first etching substep, in which the respective first part of the circuit element is structured up to a surface of a first metallic layer for the first conductor element and subsequently resulting edge regions of the first part of the circuit element are passivated through oxide deposition using a spacer technique, and a second etching substep, in which the first conductor element is respectively structured up to the upper side of the substrate region to produce a substantially common, flush, vertically extending edge of the first conductor element and the passivation.
In the general method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a multiplicity of memory cells, in particular, MRAM cells or the like, in which at least one circuit element is situated substantially in a crossing area of two conductor elements, between these elements, first a substrate region is formed. At least one first and one second conductor element are then formed on a surface area of the substrate region, so as to have at least one crossing area, whereby at least one circuit element is primarily formed between a side, facing away from the substrate region, of the first conductor elements and a side, facing the substrate region, of the second conductor element, primarily in the crossing area of the conductor elements.
In the inventive method for manufacturing a semiconductor circuit system, at least the formation, and, in particular, the structuring, of the respective circuit element is carried out, at least partially, at substantially the same time as and/or together with the formation, and, in particular, the structuring, of the first and/or second conductor element.
It is, thus, a basic idea of the invention to form the circuit elements of the semiconductor circuit system that are to be formed in crossing areas of the conductor elements, not in the context of a separate manufacturing step, but rather at the same time as and/or together with the conductor elements themselves. Thus, the process steps required for the formation of the conductor elements are made, at least in part, useful for the formation of the circuit elements themselves as well. As such, conventional manufacturing steps that are to be provided separately, and also the corresponding apparatuses, are omitted. As a result, the manufacturing method for the semiconductor circuit system is considerably simplified, which results in a savings of time and costs in manufacturing. In addition, certain adjustment or alignment difficulties and geometrical imprecisions in the formation of the corresponding positions of the circuit elements in the crossing areas of the conductor elements are avoided because the circuit elements are structured in one stroke, so to speak, with the conductor elements, in a self-adjusting process.
The inventive method is particularly preferred for manufacturing a semiconductor circuit system in the area of semiconductor memory devices, in particular, based on MRAM cells. Accordingly, memory elements are formed as circuit elements, in particular, as TMR stacks of an MRAM cell or the like.
In the formation of the substrate region, a semiconductor region is preferably formed having an insulating region and a corresponding Complementary Metal-Oxide Semiconductor (“CMOS”) structure. The system having the plurality of first and second conductor elements and having the corresponding circuit elements is then correspondingly provided on the substrate region formed as such.
In accordance with another mode of the invention, for the formation of the first conductor elements, first a first material layer or metallic layer is applied primarily on the upper side of the substrate region, in particular, over a large area or over the entire surface or in two-dimensional form, and/or, in particular, using aluminum or the like. In addition, an adhesive layer and/or diffusion barrier can also be provided on the upper side of the substrate region, e.g., through the deposition of titanium nitride (TiN).
Because the geometry is decisive for ensuring the reproducibility and comparability of the electromagnetic properties of the circuit ele
Everhart Caridad
Greenberg Laurence A.
Infineon - Technologies AG
Lee Jr. Granvill D
Locher Ralph E.
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