Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-11-04
2003-10-14
Olms, Douglas (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C711S005000, C370S414000
Reexamination Certificate
active
06633576
ABSTRACT:
The present invention relates generally to network devices with memory to store network packets.
BACKGROUND OF THE INVENTION
The function of a router is to receive, process, store and forward datagrams or packets to the appropriate destinations. In Asynchronous Transfer Mode (ATM) or cell-based routers all datagrams are the same length defined by a constant cellsize. Traditional routing devices often store a packet before forwarding it to its destination. In order to store the packets at the rate in which they arrive, the memory subsystem must be capable of writing a packet and any added overhead into memory before the next packet arrives. Often, the overhead data is a constant size and is approximately the same size as the smallest packet. For smaller packets the memory subsystem must run at a rate much higher than line rate since the packet plus its overhead must be written into memory in the same amount of time that it takes to receive the packet. Different interfaces have different line rates, that is, the rate at which datagrams are received by an interface card. Often interface cards have difficulty in keeping up with the rate of reception and processing of network packets.
SUMMARY OF THE INVENTION
Various implementations of the invention may include one or more of the following features.
It is advantageous to provide a high-speed memory architecture with a high bandwidth that can handle packets coming in at line rate.
In one aspect, the invention features an apparatus for storing network packets, including a latency sensitive packet handler for receiving network packets, a packet memory structure including a first memory bank and a second memory bank to store network packets, a latency insensitive packet processor connected to the first and second memory banks, and a memory controller connected to the first and second memory banks and to the packet handler, said memory controller including an arbitration agent which delays the packet processor from accessing one of the first and second memory banks when the packet processor is in a conflict for the same one of the first and second banks with the packet handler.
In an implementation, the arbitration agent does not delay the packet processor from accessing one of the first and second memory banks when the packet processor is not in conflict for the same one of the first and second banks with the packet handler.
In another implementation, the first and second memory banks are dual ported memories.
In another implementation, one of the first and second memory banks receives even memory addresses, and the other of the first and second memory banks receives odd memory addresses.
Another implementation further includes a second latency sensitive packet handler for writing out processed packets, wherein the second packet manager can be a direct memory access device.
In another implementation, the arbitration agent delays the packet processor from accessing the memory banks to when the packet processor is in a conflict for the same one of the first and second banks with the second packet handler.
In yet another implementation, the arbitration agent does not delay the packet processor from accessing one of the first and second memory banks when the packet processor is not in conflict for the same one of the first and second banks with the packet handler.
In another implementation, the packet processor is a multi-threaded microcontroller.
In still another implementation, a storage device for storing packets for processing by the packet processor is included, wherein the storage device can be a FIFO.
In another aspect, the invention features an apparatus for storing packets in memory for processing and routing, including means for receiving a plurality of packets having a first descriptor, means for preparing the packets for processing and routing, means for writing individual of the plurality of packets alternately into a first memory structure, and a second memory structure, means for alternately reading individual packets from the first memory structure and the second memory structure, means for processing the plurality of packets for routing, means for writing individual of the plurality of packets alternately into the first memory structure, and the second memory structure, means for alternately reading individual packets from the first memory structure and the second memory structure and means for routing the plurality of packets to a plurality of destinations.
In an implementation, the means for receiving a plurality of packets comprises a packet over SONET framer.
In another implementation, the means for preparing the packets for processing and routing includes means for classifying the packets and means for creating a second descriptor.
In yet another implementation, the means for processing the packets for routing includes means for creating a second descriptor having information relating to a plurality of destinations for the plurality of packets.
In still another implementation, the means for routing the plurality of packets to a plurality of destinations includes means for transferring the plurality of packets to a fabric ingress chip.
In another aspect, the invention features a method for storing packets in memory for processing and routing, including receiving a plurality of packets having a first descriptor, preparing the packets for processing and routing, writing individual of the plurality of packets alternately into a first memory structure, and a second memory structure, alternately reading individual packets from the first memory structure and the second memory structure, processing the plurality of packets for routing, writing individual of the plurality of packets alternately into the first memory structure, and the second memory structure, alternately reading individual packets from the first memory structure and the second memory structure, and routing the plurality of packets to a plurality of destinations.
In an implementation, receiving a plurality of packets comprises using a packet over SONET framer.
In another implementation, preparing the packets for processing and routing comprises classifying the packets and creating a second descriptor.
In another implementation processing the packets for routing comprises creating a second descriptor having information relating to a plurality of destinations for the plurality of packets.
In yet another implementation, routing the plurality of packets to a plurality of destinations comprises transferring the plurality of packets to a fabric ingress chip.
In another aspect, the invention features a method for arbitrating reads of packets into memory, including providing a memory system having a first packet handler, a packet processor, a second packet handler, a packet memory connected to the first and second packet handlers and to the packet processor, and a memory controller connected to the packet memory and to the first and second packet handlers, performing a plurality of reads with the packet processor from a plurality of memory locations in the packet memory, performing a plurality of reads with the second packet manager from the plurality of packet memory locations in the packet memory, and delaying any one of the plurality of reads performed by the packet processor when the any one of the plurality reads performed by the packet processor is to a common memory location of any one of the plurality of reads performed by the second packet manager.
In another implementation, the method further includes completing the reads by the packet processor after delaying the reads.
In yet another aspect, the invention features a method for arbitrating writes of packets into memory, including providing a memory system having a first packet handler, a packet processor, a second packet handler, a packet memory connected to the first and second packet handlers and to the packet processor, and a memory controller connected to the packet memory and to the first and second packet handlers, performing a plurality of writes using the packet processor to a plurality of memory lo
Angle Richard L.
Ladwig Geoffrey B.
Melaragni William
Fish & Richardson P.C.
Olms Douglas
Pizarro Ricardo M.
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