Memory buffer arrangement

Details Memory buffer arrangement Memory buffer arrangement

2002-06-27

2003-10-28

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S189050, C365S230080

Reexamination Certificate

active

06639820

ABSTRACT:

BACKGROUND
Data transfer rates between memory and memory controllers are ever increasing. To improve signal integrity at higher transfer rates, memory buffer devices between the memory devices and memory controllers have been introduced. See, for example, U.S. Pat. No. 6,317,352 “Apparatus for Implementing a Buffered Daisy Chain Connection Between a Memory Controller and Memory Modules”. The memory buffer devices reduce the number of devices connected to the memory bus, thus reducing the number of stubs on the memory bus which are a source of signal reflections. Further, memory buffer devices reduce the load on the memory controller by reducing the number of devices being directly driven by the memory controller. By reducing the load, the memory controller may utilize faster signal rates and/or lower signal voltages. The memory buffer devices, however, consume circuit board area. Reducing the circuit board footprint of the memory buffer devices may help satisfy the ever increasing desire for smaller form factors and increased storage capacity.


REFERENCES:
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6487102 (2002-11-01), Halbert et al.
patent: 6493250 (2002-12-01), Halbert et al.
patent: 6542393 (2003-04-01), Chu et al.

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