Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-11-01
2003-12-09
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S025000
Reexamination Certificate
active
06662134
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally related to printed circuit boards (PCB) and, more particularly, to a method and apparatus that enable connections between Joint Test Access Group (JTAG)-compliant devices installed on a PCB to be tested with an EXTEST regardless of whether or not the connections being tested are AC-coupled.
BACKGROUND OF THE INVENTION
Traditionally, Bed-Of-Nails tests have been used to test PCB connections. Such tests required that at least one test probe per integrated circuit (IC) chip pin be incorporated into the PCB to provide accessible connection points for testing. Each connection point would be tested for continuity to all other expected connection points on the PCB. This enabled defects in connections to be detected, isolated and repaired.
However, as surface mount technology has improved, the packing density of components on PCBs has improved, and placing Bed-Of-Nails fixtures on PCBs tends to defeat the advantages of packing density improvements. In an effort to enable testing to be performed in a manner that did not thwart packing improvements, a consortium known as The Joint Test Access Group (JTAG) developed a PCB testing methodology that has evolved into the current 1149.1 standard of the Institute of Electrical and Electronics Engineers (IEEE).
Rather than placing Bed-Of-Nails fixtures on the PCB, this standard defines a Boundary Scan Architecture that requires incorporation of standard hardware into integrated circuit (IC) chips to enable IC chips installed on a PCB, and the connections between output pins and expected input pins of the IC chips, to be easily tested with software. This eliminated the need for Bed-Of-Nails fixtures and thus facilitated improvements in surface mount technology and packing density.
IC chips that incorporate the Boundary Scan Architecture are typically referred to as being “JTAG-compliant”. A variety of tests can be performed on JTAG-compliant IC chips by sending specific instructions to the standard JTAG hardware incorporated into the IC chips and by evaluating the execution results with software. One of these tests, defined under the JTAG standard as the EXTEST, is used to test connections on the PCB between JTAG-compliant IC chips. During the test, boundary scan cells associated with one or more output pins of a transmitting chip are preloaded with test patterns comprised of 1s and 0s and input boundary cells associated with one or more input pins of a receiving IC chip capture the transmitted test pattern. The captured test patterns are then analyzed to determine whether they match the corresponding transmitted test patterns.
If a mismatch occurs for a particular output pin and input pin, then a defect is assumed to exist in the connection between the pins, and the defect can then be isolated and repaired. The defect may be, for example, a short circuit between paths on the PCB or an open circuit in a path. The EXTEST is used to test all of the channels on the PCB so that any connection defects between components on the PCB can be detected, isolated and repaired.
However, generally, the EXTEST does not work for systems that are AC-coupled because the test is relatively slow in terms of the rate at which the 1s and 0s are transmitted across the PCB. Because of the relatively slow rate at which the 1s and 0s of the test patterns are transmitted, AC coupling in the connection can cause logic levels to decay before they can be checked at the receiving pin. The transmission rate during testing is intentionally kept low so that propagation times across the PCB can be safely ignored.
One prior solution to the AC-coupling problem has been to use complex codes to represent the test patterns. The codes have large AC components and will pass through any AC coupling without decaying before they can be checked at the receiving pin. However, the encoding logic needed to drive the complex test patterns at the output pins and the decoding logic and timing clocks needed to decode them at the receiving pins are generally acknowledged to be too expensive.
Accordingly, a need exists for a method and apparatus that enable the EXTEST to be performed with AC-coupled systems without the need for implementing the aforementioned expensive encoding and decoding logic and timing clocks.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus are provided for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more AC-coupled connections on a printed circuit board (PCB). Direct current (DC)-restore logic receives an AC-coupled signal that corresponds to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.
The apparatus comprises direct current (DC)-restore logic that receives an AC-coupled signal corresponding to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit IC and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.
The method of the present invention comprises the steps of providing the DC-restore logic that receives the AC-coupled signal corresponding to an EXTEST test pattern that has been converted into an AC signal by AC-coupling to the connection being tested, and using the DC-restore logic to convert the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.
These and other features and advantages will become apparent from the following description, drawings and claims.
REFERENCES:
patent: 5497378 (1996-03-01), Amini et al.
patent: 5726999 (1998-03-01), Bradford et al.
patent: 6000051 (1999-12-01), Nadeau-Dostie et al.
patent: 6594802 (2003-07-01), Ricchetti et al.
patent: 6601189 (2003-07-01), Edwards et al.
Agilent Technologie,s Inc.
Hoff Marc S.
Raymond Edward
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