Memory array with address scrambling

Details Memory array with address scrambling Memory array with address scrambling

2002-01-28

2003-06-03

Pitts, Harold I. (Department: 2876)

Registers

Records

Conductive

C235S487000

Reexamination Certificate

active

06572024

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory array including a plurality of storage cells and a selection device which selects a storage cell based on a logical address supplied via an address bus, and in particular to a memory array in which the selection device includes a scrambling device for scrambling a relationship between logical addresses received from an address bus and physical addresses of the storage cells to which physical access is sought.
2. Description of Related Art
Memory arrays of the type with which the present invention is concerned are part of all common microcomputers and described e.g. in “Chip und System,” R. Zaks, SYBEX-Verlag, 1984, pp. 133ff. Basically similar microcomputers are also used in security-relevant applications, e.g. smart card systems for performing financial transactions. However, in these cases additional measures are regularly taken to prevent attaches on security by manipulation of the microcomputer. An example of such a measure is found in “Chipkarten,” Karlheinz Fietta, Hüthig Verlag, 1989, pp. 68 to 72. In the TS 1834 chip from THOMSON described therein the address bus and data bus are made invisible from the outside by means of an interface. Another measure for increasing the tamperproofness of the microcomputer can be found in EP 694 846 A1. It is provided here that the data transmitted via the data bus arc scrambled possibly several times so that it is impossible to evaluate and thus manipulate the data even if one succeeds in reading them.
Although known measures already guarantee a high degree of security, it is desirable in view of the special importance of the security of microcomputers used in connection with performing financial transactions to improve their tamperproofness further. The invention is based on the problem of providing further measures that achieve this.
SUMMARY OF THE INVENTION
The problem is solved by an array and a method, in which at least one random-access memory present in the microcomputer is preceded by a scrambling device which allocates cells in the memory in unpredictable fashion to the logical addresses transmitted via the address bus, said cells then being actually occupied physically. The inventive memory array thus offers the advantage of making it impossible to manipulate the microcomputer by analyzing the contents of the storage cells of the random-access memory. The logic required for realizing the scrambling device requires little space and ca be readily included in common microcomputer fabrications. Scrambling is preferably repeated regularly in response to defined events.


REFERENCES:
patent: 5765197 (1998-06-01), Combs
PCT/EP00/4285, Nov. 5, 2000.

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