Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-10-31
2003-08-05
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189090, C365S203000
Reexamination Certificate
active
06603681
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of pulse programming, in particular for memory devices exhibiting a high parallelism.
The invention also relates to a device implementing the method.
The invention relates, particularly but not exclusively, to a non-volatile memory, and the detailed description that follows will make reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As is well known, in a memory device that uses floating-gate MOS transistors as basic memory cells, the threshold voltage of the floating-gate transistor is modulated in order to discriminate between two logic states, namely: a state where the floating gate contains no charge and that is characteristic of a UV-erased cell (corresponding to a stored logic “1”); and a state where the floating gate contains a sufficient number of electrons to raise the threshold level, thus indicating a programmed cell condition (corresponding to a stored logic “0”).
To read from a memory cell
1
, a current reading method may be used by applying a read voltage Vread to the control gate terminal of the cell and reading the current that flows through the cell:
if the cell is written, its threshold voltage will be higher than the read voltage Vread, and no current is flowing through the cell;
if the cell is erased, its threshold voltage is adequate to allow a current flow.
The probabilistic distribution of the threshold voltages of memory cells, and their digital equivalence, are shown schematically in
FIG. 1A
for of a two-level EEPROM Flash cell.
To read information from memory cells of this type, a sense amplifier is used to compare the cell current with a reference current value and to convert the analog information of the addressed data contained in the cell (i.e. the threshold voltage value of the cell) into a digital form (i.e. a logic “0” or “1”).
Non-volatile multilevel memories have recently made their appearance on the market, these being memories where plural information bits can be stored in each cell. In memories of this kind, the charge contained in the floating gate is further split into a number 2
nb
of distributions, where “nb” is the number of bits to be stored into a single cell. For example, where two bits per cell are provided, the sense amplifier must deal with four distributions instead than two distributions as in the two-level case, as shown schematically in
FIG. 1B
for a two bits multilevel EEPROM Flash cell.
It should be noted that the working range of the threshold voltage is unrelated to the number of bits that a cell is to contain. Using a multilevel structure involves, therefore, a reduction of the distances separating the various distributions threshold-wise.
Reducing the distances between the threshold voltage distributions means reducing the current differences that the sense amplifier must sense. Moreover, a specific programming method must be used for setting the cells within the different voltage distributions.
The exemplary instance of a NOR architecture Flash EEPROM will be considered here below for simplicity.
As is well known, memory cells of this kind are written by hot electron injection, by applying a 10 V potential to the control gate terminal, a 5 V potential to the drain terminal and by connecting the source terminal to a ground reference, the floating gate terminal is allowed to store charge up to its saturation state.
In a multilevel memory, because of the reduced differences between the threshold voltages that correspond to the various charge levels that the floating gate terminal can accept, and to the differences between the various conduction levels of the cells, the cell programming phase requires a great accuracy control, and especially a control of the charge stored into the floating gate terminal during that programming phase.
It has been shown, both in theory and experimentally, that a linear relation exists between the variation &Dgr;VG of the voltage applied to the control gate terminal during the cell programming phase and the threshold jump obtained at set values of both the voltage VD applied to the drain terminal and the voltage VS applied to the source terminal, as discussed by Riccò et al. in an article “Nonvolatile Multilevel Memories For Digital Application”, Pro. IEEE, December 1998, vol. 86, pages 2399-2421.
As shown schematically in
FIG. 2
, the cell should be programmed by applying a linearly increasing voltage to its control gate terminal.
In practice, using a series of program pulses which vary by a constant value &Dgr;VG is equally advantageous. The programming voltage would be here a constant-pitch stepped ramp.
It can be appreciated that a distribution of the threshold voltage having a width &Dgr;VG, i.e. the same pitch as the stepped programming voltage, can be obtained by the above programming method.
In that way, multilevel memory cells can be programmed using a desired threshold voltage value and a minimum number of program pulses.
A major problem is that the above cell programming method is inherently a slow one: a succession of pulses must be applied to the control gate terminal of the cell, which takes longer than the single program pulse supplied to two-level cells.
In order to achieve a single byte program time comparable with that of a conventional two-level cell, it has been used programming in parallel several multilevel cells.
If the programming time a single byte is 8 &mgr;s in the two-level case, and it takes 200 &mgr;s to run the full programming steps in the multilevel case, then an effective programming time of 6 &mgr;s per byte in multilevel cells can only be obtained by simultaneously programming 256 bits in multilevel cells.
This results in an increased internal parallelism of multilevel memory devices thus raising problems with their internal configurations.
Well employed by commercially available devices is the synchronous reading mode (burst mode), in order to improve the transfer of data between the memory and the host system. The term “synchronous” originates from that the data is to be output synchronously with an external clock signal. The frequency of the clock signal usually exceeds that for the asynchronous access time. The clock signal frequency lies usually in the 50 MHz range, whereas the access time of memory devices is in the 100 ns (10 MHz) range. It's thus necessary to read internally a much longer binary word than the output word, so as to create a “buffer” for different periods of the clock signal.
To increase the size of the internal word means to increase the number of bits that must be read in parallel, and therefore, the number of sense amplifiers in the memory device.
Thus, there is a demand for memory architectures featuring high parallelism at the reading and programming phases. The demand is even more pressing where multilevel memory devices are concerned.
Shown in
FIG. 3
is a typical architecture for a non-volatile memory
1
. In particular, the memory array comprises a number of sectors
2
divided into two groups, A and B. Each group has a row decoder
3
A,
3
B and a sense amplifier array
4
A,
4
B of its own (SA<0> . . . SA<7>).
In the architecture shown, there are eight sense amplifiers, to communicate a binary word of one byte (eight bits) to the outside world. The sense amplifier arrays
4
A,
4
B are enabled exclusively according to which part (either A or B) of the memory array is to be read or programmed. The digital outputs from the sense amplifiers are passed into a multiplexer
5
for routing to the output pads.
Actually, although there are eight bits to be read, as many as sixteen sense amplifiers have been connected in order to limit the parasitic load seen by them from the bit-line side.
Assume that 64 cells are to be read in parallel. Proceeding by the above technique would be difficult because doubling the number of sense amplifiers means adding as many as 64 elements within the step of two sectors
2
; or quadruplicating them within the step of a s
Micheloni Rino
Sacco Andrea
Iannucci Robert
Jorgenson Lisa K.
Le Thong
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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