Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-02-20
2003-12-09
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S531000
Reexamination Certificate
active
06661079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention relates to capacitors and, more particularly, to a semiconductor-based spiral capacitor.
2. Description of the Related Art.
A capacitor is a device with two conductors separated by a dielectric that accumulates and holds an electric charge. Capacitors are common circuit elements and are frequently used in semiconductor devices. Semiconductor-based capacitors include lateral flux capacitors, vertical flux capacitors, and combined lateral and vertical flux capacitors.
FIG. 1
shows a cross-sectional view that illustrates a prior art lateral flux capacitor
100
. As shown in
FIG. 1
, lateral flux capacitor
100
includes a first metal trace T
1
, a second metal trace T
2
, and a dielectric region
112
that is formed between metal traces T
1
and T
2
. Metal traces T
1
and T
2
are formed from the same layer of metal, and are horizontally separated from each other. In this configuration, the flux lines are lateral, and go from trace T
1
to trace T
2
when trace T
1
is positive with respect to trace T
2
.
FIG. 2
shows a cross-sectional view that illustrates a prior art vertical flux capacitor
200
. As shown in
FIG. 2
, vertical flux capacitor
200
includes a first metal trace T
1
, a second metal trace T
2
, and a dielectric region
212
that is formed between metal traces T
1
and T
2
. Metal traces T
1
and T
2
are formed from adjacent layers of metal, and are vertically separated from each other. In this configuration, the flux lines are vertical, and go from trace T
2
to trace T
1
when trace T
2
is positive with respect to trace T
1
.
FIG. 3
shows a cross-sectional view that illustrates a prior art lateral and vertical flux capacitor
300
. As shown in
FIG. 3
, lateral and vertical flux capacitor
300
includes a number of first metal traces T
1
, a number of second metal traces T
2
, and a dielectric region
312
that is formed between metal traces T
1
and T
2
.
The first metal traces T
1
are formed from a first layer of metal to be horizontally separated from each other, while the second metal traces T
2
are formed from an adjacent layer of metal to be horizontally separated from each other, and vertically separated from the first metal traces T
1
. Further, the polarity of the metal traces alternates both is horizontally and vertically. In this configuration, both lateral and vertical flux lines are present.
One problem with semiconductor-based capacitors is that semiconductor-based capacitors can be quite large and consume significant amounts of silicon real estate. As a result, a number of approaches have been used to increase the capacitive density of a capacitor to thereby reduce the size of the capacitor.
FIG. 4
shows a plan view that illustrates a prior art capacitor
400
that has an increased capacitive density. As shown in
FIG. 4
, capacitor
400
includes a first metal trace T
1
, a second metal trace T
2
, and a dielectric region
412
that is formed between metal traces T
1
and T
2
. Metal traces T
1
and T
2
are formed from the same layer of metal, horizontally separated from each other, and interdigitated. In this interdigitated configuration, capacitor
400
provides substantially more capacitance per unit of area than does capacitor
100
.
FIG. 5
shows a plan view that illustrates a prior art capacitor
500
that also has an increased capacitive density. As shown in
FIG. 5
, capacitor
500
, which has a weave structure, includes a number of first metal traces T
1
, a number of second metal traces T
2
, and a dielectric region
512
that is formed between metal traces T
1
and T
2
.
The first metal traces T
1
are formed from a first layer of metal to be horizontally separated from each other, while the second metal traces T
2
are formed from an adjacent layer of metal to be horizontally separated from each other, and vertically separated from the first metal traces.
In addition, the second metal traces T
2
are orthogonally-oriented with respect to the first metal traces T
1
, while the polarity of the metal traces in each layer horizontally alternates. Further, vias V are used to vertically interconnect metal traces which have the same polarity. This configuration provides increased capacitance per unit area, but with less inherent series inductance.
Other structures, such as fractal capacitors, have also been used. Although semiconductor-based capacitors can be formed as described above, there is a need for an alternate capacitor structure that provides a high capacitance per unit area.
SUMMARY OF THE INVENTION
The present invention provides a capacitor that is formed in a semiconductor material of a first conductivity type. A capacitor in accordance with the present invention includes a first layer of isolation material that is formed on the semiconductor material, and a first metal trace that is formed on the first layer of isolation material. The first metal trace has a first center point, a first end point, and a spiral shape with loops that extends away from the first center point to the first end point.
The capacitor also includes a second metal trace that is formed on the first layer of isolation material. The second metal trace has a second center point, a second end point, and a spiral shape with loops that extends away from the second center point to the second end point. The second metal trace is formed between the loops of the first metal trace, and around the first metal trace.
A capacitor in accordance with the present invention also has a plurality of layers of isolation material that are formed over the semiconductor material. A first layer of isolation material is formed on the semiconductor material. Other than the first layer of isolation material, each layer of isolation material is formed on a preceding layer of isolation material.
The capacitor further has a plurality of spaced apart metal layers that correspond to the plurality of layers of isolation material. Each metal layer is formed on a corresponding layer of isolation material and has a first metal trace and a second metal trace. The first metal trace has a first center point, a first end point, and a spiral shape with loops that extends away from the first center point to the first end point.
The second metal trace has a second center point, a second end point, and a spiral shape that extends away from the second center point to the second end point. The second metal trace is formed between the loops of the first metal trace, and around the first metal trace.
The capacitor additionally has a plurality of vias that are formed in the second and greater layers of isolation material. The vias make electrical connections between each vertically adjacent first metal trace, and each vertically adjacent second metal trace.
Further, the capacitor can also include a plurality of first bridges that are formed on a top layer of isolation material over loops of a first metal trace of a top layer of capacitor metal. The capacitor can additionally include a plurality of first bridge vias that make an electrical connection with the first bridges and loops of the first metal trace of the top layer of capacitor metal.
The capacitor can further include a plurality of second bridges that are formed on the top layer of isolation material over loops of a second metal trace of the top layer of capacitor metal, and a plurality of second bridge vias. The second bridge vias make an electrical connection with the second bridges and loops of the second metal trace of the top layer of capacitor metal.
REFERENCES:
patent: 5111169 (1992-05-01), Ikeda
patent: 6297524 (2001-10-01), Vathulya et al.
patent: 6383858 (2002-05-01), Gupta et al.
Hirad Samavati et al., “Fractal Capacitors”, IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pps. 2035-2041.
Roberto Aparicio and Ali Hajimiri, “Capacity Limits and Matching Properties of Lateral Flux Integrated Capacitors”, Department of Electrical Engineering, California Institute of Technology, Pasadena, CA, IEEE 2001 Custom Integrated Circuits Confer
National Semiconductor Corporation
Nguyen Cuong
Pickering Mark C.
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