Register selection system and method

Details Register selection system and method Register selection system and method

1996-08-06

1999-02-23

Sheikh, Ayaz R.

Boots, shoes, and leggings

36471606, 364768, 365195, G06F 1700, G06F 750, G11C 700

Patent

active

058751211

ABSTRACT:
A register selection system increases a speed for selection of memory registers when selection is based upon a constant K defined by a sum of two numbers. The register selection system includes a specialized predecoder interconnected with a specialized decode array. The predecoder has first and second address inputs. The predecoder is configured to process first and second address values each of width n on the first and second address inputs respectively in order to produce first, second, third, and fourth predecoded values of width n on respective predecoder outputs. The first, second, third, and fourth predecoded values have respective widths of n+1, n, n, n-1. The decode array, which is connected to the predecoder outputs, is configured to receive the predecoded values. The decode array has 2.sup.n+1 register select outputs corresponding respectively with registers. The decode array is configured to assert one of the register select outputs, while deasserting a remainder of the register select outputs, based upon the predecoded values. As a result, a determination is made as to when the two numbers equal the constant K without performing a summing operation and a carry propagation associated with the summing operation. Moreover, a selection of the one register is accomplished based upon the determination.

REFERENCES:
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patent: 4831570 (1989-05-01), Abiko
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patent: 5305249 (1994-04-01), Yoshida
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5600583 (1997-02-01), Bosshart
patent: 5631860 (1997-05-01), Morinaka

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