Semiconductor wafer test system

Details Semiconductor wafer test system Semiconductor wafer test system

2001-07-17

2003-08-05

Niebling, John F. (Department: 2812)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06603316

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a system and method for carrying out a non-contact burn-in test on a semiconductor wafer.
Recently, the annual production of semiconductor devices has been rocketing year after year. Generally speaking, the greater the number of devices produced per unit time, the greater the number of devices with infant mortality to be screened out therefrom by an accelerated life test called “burn-in”, for example. As is well known in the art, a burn-in test is carried out on semiconductor devices by subjecting the devices to an elevated temperature under an electrical power stress. Some of the devices that failed to withstand the stress are screened out as NO-GOs, while the other devices that could endure the stress successfully are shipped as GOs, or good products. Over the past few years, however, the time afforded to develop new semiconductor devices has been more and more limited. So the burn-in test should also be finished in a shorter amount of time. In addition, a wafer test system for use in such a burn-in test also has to have its size further reduced, since the devices under test have been downsized almost day after day.
The burn-in test has normally been carried out by applying a stress voltage onto semiconductor devices on a wafer with probe pins brought into contact with the devices under test.
FIG. 14
illustrates how the burn-in test is carried out on a semiconductor wafer
301
including a great number of semiconductor devices thereon using a known wafer test system. As shown in
FIG. 14
, the wafer
301
, supported on a substrate plate
302
, is brought into contact with probe pins extending from a probe card
303
, and then supplied with a signal delivered from a tester
304
through the pins of the card
303
.
Next, it will be described how the wafer test system operates. In the example illustrated in
FIG. 14
, the plate
302
is grounded at a potential level of 0 V. The wafer
301
is in electrical contact with the plate
302
, and each of the numerous devices on the wafer
301
also has its substrate potential fixed at 0 V. In such a state, the tester
304
outputs a signal to devices under test on the wafer
301
by way of the pins of the card
303
. The devices under test, which are in contact with the pins of the card
303
, start to operate in response to the signal supplied from the tester
304
. As a result, a voltage is applied onto the gate electrode of each of those devices (i.e., transistors). That is to say, a voltage stress is generated between the gate electrode of the transistor and the substrate thereof. In this manner, the devices on the wafer
301
are subjected to the burn-in.
However, if test terminals provided for semiconductor devices on a wafer are of a different type from those provided for devices on another wafer, then the known wafer test system should prepare two mutually different types of probe cards for these two wafers.
SUMMARY OF THE INVENTION
To avoid such an undesirable situation, the present inventor performed a non-contact burn-in test on semiconductor devices on a semiconductor wafer without using any probe pins. In this burn-in test, each of the devices under test on the wafer was exposed to a direct-current (DC) electric field so that a voltage was applied onto the gate oxide film of the devices. Hereinafter, with reference to
FIG. 10
, I will briefly describe the burn-in test I conducted before describing the summary of my invention.
FIG. 10
illustrates a semiconductor wafer test system that I used for the burn-in test. First, the respective elements of the system will be described.
As shown in
FIG. 10
, a semiconductor wafer
501
, including a great number of semiconductor devices under the burn-in test, is supported on a substrate plate
502
. The burn-in test is carried out by applying a predetermined voltage from a DC power supply
504
to a conductive plate
500
and by exposing the devices under test on the wafer
501
to an electric field S
500
that has been created from the conductive plate
500
. The electric field S
500
created from the conductive plate
500
has an intensity proportional to the voltage applied from the power supply
504
. As a result, a current I
501
flows from the plate
502
into the ground.
FIG. 11
illustrates one of the devices under the burn-in test on the wafer
501
to a larger scale. First, the respective elements of the device will be described. As shown in
FIG. 11
, the semiconductor device (i.e., an MOS transistor in this case) to be exposed to the electric field S
500
created from the conductive plate
500
has been electrically isolated from adjacent devices by isolation regions
501
e
and
501
f.
The device includes gate electrode
501
a
, gate oxide film
501
b
, source/drain regions
501
c
and
501
d
and p-well
501
g
. That is to say, part of the wafer
501
for this device includes the source/drain regions
501
c
and
501
d
, p-well
501
g
and substrate portion
501
h.
As also shown in
FIG. 11
, the wafer
501
is supported on the substrate plate
502
. The device is exposed to the electric field S
500
that has been created from the conductive plate
500
by applying a voltage from the DC power supply
504
to the conductive plate
500
. A parallel plate capacitor is formed between the conductive plate
500
and gate electrode
501
a
and another parallel plate capacitor is formed between the gate electrode
501
a
and p-well
501
g
. A leakage resistor
512
exists between the gate electrode
501
a
and the ground and a current I
501
flows from the substrate plate
502
into the ground. In
FIG. 11
, only one n-channel MOS transistor is illustrated as one of the great many devices on the wafer
501
for the sake of simplicity. Accordingly, the source/drain regions
501
c
and
501
d
have been doped with an n-type dopant, while the p-well
501
g
and substrate portion
501
h
are of p-type.
The substrate portion
501
h
is in electrical contact with the grounded substrate plate
502
and is fixed at 0 V. The p-well
501
g
is in contact with the substrate portion
501
h
and these regions
501
g
and
501
h
are both of p-type. So the p-well
501
g
is also fixed at 0 V.
When a voltage V
0
(V) is applied to the conductive plate
500
, the electric field S
500
is created, thereby polarizing the gate electrode
501
a
and producing a voltage Va
0
(V) at the gate electrode
501
a
. As a result, an electric field stress Ea (V/m) corresponding to the voltage Va
0
(V) is placed on the gate oxide film
501
b
. Hereinafter, this stress will be analyzed quantitatively.
Suppose the area of the gate electrode
501
a
is Sa (m
2
), the distance between the conductive plate
500
and gate electrode
501
a
is d
1
(m), the thickness of the gate oxide film
501
b
is d
2
(m), the permeability between the conductive plate
500
and gate electrode
501
a
is &egr;
1
(C/(V·m)) and the permeability of the gate oxide film
501
b
is &egr;
2
(C/(V·m)). To simplify the computation, one parallel plate capacitor
510
is supposed to be formed between the conductive plate
500
and gate electrode
501
a
and another parallel plate capacitor
511
is supposed to be formed between the gate electrode
501
a
and p-well
501
g
as schematically illustrated in FIG.
12
.
As also shown in
FIG. 12
, a voltage is applied from the DC power supply
504
to the conductive plate
500
, thereby creating the electric field to which the device under test is exposed. A leakage resistor
512
exists between the gate electrode
501
a
and the ground.
Suppose no current flows through the resistor
512
for a while after the voltage V
0
(V) has been applied to the conductive plate
500
. Then, a quantity Q
0
(C) of charge stored on the parallel plate capacitor
510
is given by the following Equation (1):
Q
0
=&egr;
1
·
S/d
1
×(
V
0
−
Va
0
)  (1)
where Va
0
(V) is the voltage induced at the gate electrode
501
a.
The charge quantity Q
0
can also be obtained by the following Equation (2) using the quantit

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