Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-04-26
2003-10-21
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S842000, C029S852000, C029S830000, C029S882000, C324S758010, C324S756010, C324S765010
Reexamination Certificate
active
06634100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an interposer configured to receive a semiconductor device for testing. More specifically, the invention pertains to such a test interposer having an alignment fence for receiving and aligning semiconductor devices, such as flip-chip type semiconductor dice, ball grid array (BGA) packages, and chip scale packages (CSPs), with test sockets of the interposer. The present invention also relates to methods for fabricating such a test interposer.
2. State of the Art
The semiconductor industry produces extremely large numbers of miniature electrical devices, or “chips” or dice, which are referred to as semiconductor devices. Semiconductor devices are installed in essentially every electronic device. Such devices are typically fabricated in large numbers on a wafer of semiconductive material (e.g., silicon, gallium arsenide, or indium phosphide). The individual chips or dice are then singulated from the wafer.
Tests are typically performed at several stages of manufacture for the purposes of evaluating the electrical characteristics of various circuits of the semiconductor devices and for detecting electrical, structural, and other types of faults in the semiconductor devices. These tests are sometimes performed on representative semiconductor devices and sometimes on each semiconductor device of a certain type, depending on the criticality of use, manufacturing costs, and expectation of flaws.
Conventionally, the semiconductor industry favored a “final” electrical testing of semiconductor devices, which was effected before semiconductor devices were packaged with electrical leads extending therefrom and encapsulated in a protective material. However, it is now recognized that conventional packaging processes may cause significant numbers of semiconductor devices to fail. For example, as a semiconductor device is being encapsulated, the protective material may cause particulate die coat penetration, “bond wire sweep”, which may break electrical connections made by the bond wires or cause electrical shorts between adjacent bond wires, and other problems. Accordingly, it is desirable to test semiconductor devices after they have been packaged.
Some state of the art semiconductor devices lack conventional packages (e.g., leads and encapsulants) or are minimally packaged. Flip-chip type semiconductor devices may be left unpackaged and connected directly to a higher level substrate by way of conductive structures, such as solder balls, disposed between the bond pads of the flip-chip and corresponding contact pads of the higher level substrate.
Ball grid array packages, a type of flip-chip semiconductor device, may include a semiconductor die disposed on and electrically connected to an interposer. The interposer has contact pads on the opposite side thereof that are arranged in a pattern complementary to that of contact pads on a higher level substrate to which the ball grid array package is to be connected. The interposer may also include electrical traces that lead to contact pads arranged in a different pattern than the bond pads of the semiconductor die and, therefore, reroute the bond pads of the semiconductor die.
Another type of state of the art package is the so-called “chip scale package”, wherein the dimensions of the total package are only slightly larger than the dimensions of the semiconductor die thereof A chip scale package typically includes a flip-chip type semiconductor die with one or more thin layers of protective material (e.g., plastic encapsulant) on the active surface thereof Conductive structures (e.g., solder bumps) protrude from bond pads of the flip-chip type semiconductor die and extend above the layer of protective material. Chip scale packages may also have one or more thin layers of protective material on the edges or backsides of the semiconductor dice thereof Ball grid array packages may be formed as chip scale packages.
When these types of semiconductor devices are tested, the solder bumps or other conductive structures protruding therefrom may not properly align with the corresponding test sockets of a test substrate so as to establish adequate electrical contacts between the tested semiconductor device and the test substrate. Moreover, if misalignment occurs, the conductive structures may be damaged.
In order to reduce potential damage to conductive structures, such as solder bumps, during the testing of flip-chip type semiconductor devices, interposers have been used between a test substrate and a semiconductor device to be tested. These interposers may comprise micromachined silicon or ceramic structures that include metal-lined recesses for receiving conductive structures of a semiconductor device to be tested, metal-filled vias extending from the bottom of each recess to the opposite, bottom side of the interposer, and conductive structures, such as solder bumps, communicating with the metal-filled vias and protruding from the bottom side of the interposer. The recesses of the interposer are configured to receive the conductive structures of a semiconductor device to be tested without stressing or damaging the conductive structures. The metal lining of and metal-filled via communicating with each recess facilitates electrical communication between a conductive structure disposed in each recess and the corresponding, underlying conductive structure protruding from the bottom of the interposer. The conductive structures of the interposer are precisely aligned with test pads or sockets of a test substrate so as to establish an electrical connection between a semiconductor device assembled with the interposer and the test substrate. The test pads or sockets of the test substrate communicate with known semiconductor device test equipment.
Nonetheless, the conductive structures protruding from a semiconductor device to be tested may be damaged when assembled with such an interposer. Moreover, since the recesses of such interposers are configured to receive the conductive structures of a semiconductor device without stressing, deforming, or otherwise damaging the conductive structures, the interposer may fail to make adequate electrical connections between some of the conductive structures and their corresponding test pads or sockets of the test substrate. Moreover, test interposers typically lack any alignment component other than the recesses thereof.
Accordingly, it appears that the art is lacking a structure for aligning the conductive structures of a semiconductor device with corresponding test pads or sockets of a test substrate without stressing or damaging the conductive structures while facilitating adequate electrical connections between the conductive structures and the test pads or sockets.
In the past decade, a manufacturing technique termed “stereolithography”, also known as “layered manufacturing”, has evolved to a degree where it is employed in many industries.
Essentially, stereolithography as conventionally practiced involves the use of a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materia
Akram Salman
Farnworth Warren M.
Wood Alan G.
Arbes Carl J.
Trinh Minh
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