Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-11-16
2003-08-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S127000
Reexamination Certificate
active
06610559
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
This invention relates generally to a method of assembling a semiconductor chip electrically and mechanically connected to a substrate, particularly in a flip chip configuration.
Assembly of solder bumped chips such as flip chip or chip scale package (SCP) is an emerging technology which satisfies the demands of the ever-increasing requirements for high I/O density, small form factor, and improved performance in integrated circuit (IC) design. In the process of chip assembly, a chip is mounted on a substrate with any kind of interconnect material. Among the many kinds of interconnect materials, solder has remained a predominant choice. Solder bumped chip assembly consists two major steps: (1) chip soldering and (2) underfill encapsulation. To attach chip to the substrate, a flux is applied to the substrate or solder bumps on the chip. The chip is then aligned with the bond pads on the substrate, placed, and reflowed, forming electrical connections and mechanical joints between flip chip and substrate. After soldering a solvent cleaning step is usually involved to remove the flux residue which otherwise weakens the underfill adhesion which in turn degrades solder joint reliability. The cleaning process is a difficult operation, often costly and time consuming, involving solvents and expensive equipments. Therefore, there is a need to develop a new technology that does not require this cleaning process.
Another issue in the implementation of solder bumped chip technology when applied to organic polymer substrate is the mismatch of the coefficient of thermal expansion (CTE) of the chip, and that of the substrate having a higher CTE. The build up stress on solder joints upon thermal excursions experienced during the application of the device causes solder joint fatigue and leads to the failure of the interconnect joints. To minimize this problem, an underfill material is applied in the interspace of chip and substrate after chip soldering to assure the reliability and electric integrity. The traditional underfill material is typically a highly flowable liquid formulation, containing filler particles to reduce CTE. The underfill material is dispensed along the edges of the chip and allowed to wick into the space between the substate and the chip. The capillary action allows the underfill to flow out to the opposite sides of the chip and completely fill the gap between the chip and the substrate. Even though the substrate is usually heated to an elevated temperature to facilitate the underfill flow, the process still takes more than seconds to completely underfill the chip, which is considered a bottle neck in manufacturing process. After underfilling, the package is subjected to an elevated temperature for underfill curing. The cured underfill material redirects or redistributes the stress away from tiny solder joints, thus enhancing the package reliability. In addition, underfill materials also serve as mechanical and environmental protection, which increases the resistance to shock, vibration, moisture, solvent, and provide thermal dissipation between chip and substrate.
While traditional capillary flow underfill materials with reduced flow and cure time are dominant in current underfill applications, the use of so-called pre-deposit fluxing underfill offers an attractive alternative which would speed up package processing and enhance compatibility with surface mount technology (SMT). In addition to bearing the functions provided by traditional underfill encapsulant, the pre-deposit underfill materials are integrated with fluxing capability. The overall assembly process based on this type of underfill material is simplified by combining three basic steps: (1) underfill dispensing, (2) chip placement, and (3) reflow. During reflow, the fluxing agent incorporated in underfill materials provides sufficient activity to remove surface oxide on solder bumps and bond pads, forming interconnect joints. In the meantime, the underfill material is chemically crosslinked, forming a strong network structure providing mechanical and environmental protection as described for traditional underfill encapsulation. The benefits of the pre-deposit underfill process are well explored in the recent years. These include simpler process to control, higher throughput, self-fluxing action, etc. Even though there has been an explosion of interest and great effort to develop this technology throughout the past decade, the use of pre-deposit underfill is, however, not without its inherent problems and limitations. One of the obstacles which pre-deposited fluxing underfill materials must overcome, is placement of the component without void entrapment. A direct consequence of underfill pre-deposit followed by fast paced chip placement (less then a second), is that the underfill material is forced to flow toward the periphery of the chip in such a short time that air is entrapped around solder bumps (FIG.
2
). These air bubbles will generate internal vapor pressure when the temperature increases during reflow, leading to process failures such as chip float and misalignment of solder bumps relative to the matching bond pads. Furthermore, the trapped air bubbles around solder joints pose a great threat to the solder joint performance, defects such as irregularity, solder extrusion, incomplete wetting, voids inside joint are often encountered. Yet, another challenge of developing such pre-deposit fluxing underfill materials is the interference of inorganic filler particles on soldering during reflow as solid filler particles will inhibit the solder wetting on bonding pads. How to incorporate fillers into pre-deposit fluxing underfill to reduce CTE and apply such pre-deposit underfill in manufacture processing remains uncertain. As a result, the pre-deposit underfill typically contains no filler, thus has a CTE much higher than that of capillary flow underfill and therefore unparallel performance.
It would be desirable to develop a method that takes advantages of capillary flow underfill process, such as void free, low CTE, widely accepted industry processing practice, and combines the attractive features of fluxing underfill such as shorter manufacturing cycle, no cleaning step required, underfill cured in the same step as solder reflow, and SMT processing compatibility. Such a processing method should yield overall higher efficiency, and low cost without compromising the reliability and performance.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a method of assembling a substrate and an IC die in a flip chip configuration using a tacky thermosettable flux and underfilling such a device. According to the present invention, as described in the illustrated embodiments, a thin layer of tacky flux is applied to the substrate or preferably to the solder bumps, a chip is placed on the substrate with the solder bumps in contact with the matching bonding pads. The tacky flux provides temporary adhesive bonding to immobilize the chip. An underfill is then dispensed along the edges of the chip and the whole package is transferred to reflow process. During solder reflow process, three major processing tasks are accomplished in one single step: (1) the underfill flows into the gap between chip and substrate and completely fills the interspace, (2) the tacky flux activates the bonding surface and facilitates solder reflow and joint formation, (3) underfill curing. Because tacky flux is formulated to be compatible with underfill, it is chemically incorporated into the cured underfill network structure.
In one aspect of present invention there is provided an integrated method of underfilling a device on a substrate during reflow process. The method comprises applying tacky flux to solder bumps or substrate to be joined and placing the chip on substrate so that the chip is temporarily held in place. The underfill is deposited on the substrate along the edges of the chip and t
Lee Ning-Cheng
Wang Shanger
Yin Wushing
Dang Phuc T.
Indium Corporation of America
Nelms David
Weingarten Schurgin, Gagnebin & Lebovici LLP
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