Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-08-09

2003-10-28

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S103000

Reexamination Certificate

active

06639445

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to level shifter circuits in semiconductor integrated circuits.
2. Conventional Technology
FIG. 2
shows a level shifter of a conventional example.
In
FIG. 2
, an inverter circuit
20
is composed of a Pch transistor
23
and an Nch transistor
28
, a level shifter circuit
21
is composed of Pch transistors
24
and
25
and Nch transistors
29
and
30
, and a level shifter circuit
22
is composed of Pch transistors
26
and
27
and Nch transistors
31
and
32
. In here, the inverter circuit
20
is connected between a VDD potential and a GND potential. The level shifter circuit
21
is connected between a VPP potential that is higher than the VDD potential and the GND potential. The level shifter circuit
22
is connected between the VPP potential and a VBB potential that is lower than the GND potential.
An operation of the above is described.
When a potential of an input signal is at the VDD potential, the Nch transistor
29
turns off and the Nch transistor
30
turns on, such that a node
35
shifts to the GND potential and a node
34
shifts to the VPP potential. In response thereto, the Pch transistor
26
turns off and the Pch transistor
27
turns on, such that a node
36
shifts to the VBB potential and an output shifts to the VPP potential. In this case, as the Pch transistors
23
and
25
and the Nch transistor
32
are turned off, no through current flows in five paths among the power supplies.
Next, when a potential of an input signal is at the GND potential, the Nch transistor
29
turns on and the Nch transistor
30
turns off, such that the node
34
shifts to the GND potential and the node
35
shifts to the VPP potential. In response thereto, the Pch transistor
26
turns on and the Pch transistor
27
turns off, such that the node
36
shifts to the VPP potential and an output shifts to the VBB potential. In this case, as the Pch transistor
24
and the Nch transistors
28
and
31
are turned off, no through current flows in the five paths among the power supplies.
In this manner, input signals between the VDD potential and the GND potential can be level-shifted to output signals between the VPP potential and the VBB potential.
In the conventional technology described above, the circuit structure is particularly complex, and therefore a problem exists in that there are restrictions in terms of layout particularly when the circuit is used as a driving circuit for word lines in flash memories and dynamic memories.
The present invention solves such problems, and one object is to provide a structure for level shifters which simplifies complex circuit structures and is not constrained by the layout.
SUMMARY OF THE INVENTION
A semiconductor integrated circuit in accordance with the present invention converts input signals composed of first and second power supply potentials to output signals composed of third and fourth power supply potentials. The semiconductor integrated circuit comprises: first, second and third Pch transistors and first, second and third Nch transistors, wherein a first terminal of the first Pch transistor connects to the third power supply potential, a first terminal of the second Pch transistor connects to the third power supply potential, a first terminal of the third Pch transistor connects to the first power supply potential, a first terminal of the first Nch transistor connects to the second power supply potential, a first terminal of the second Nch transistor connects to the fourth power supply potential, a first terminal of the third Nch transistor connects to the fourth power supply potential, a second terminal of the first Pch transistor connects to a second terminal of the first Nch transistor, a second terminal of the second Pch transistor connects to a second terminal of the second Nch transistor, a second terminal of the third Pch transistor connects to a second terminal of the third Nch transistor, a gate terminal of the first Pch transistor connects to the second terminal of the second Pch transistor, a gate terminal of the second Pch transistor connects to the second terminal of the first Pch transistor, a gate terminal of the third Pch transistor connects to an input terminal, a gate terminal of the first Nch transistor connects to the input terminal, a gate terminal of the second Nch transistor connects to the second terminal of the third Pch transistor, a gate terminal of the third Nch transistor connects to the second terminal of the second Pch transistor, and the second terminal of the second Pch transistor is an output terminal.
With the construction described above, the gate terminals of the Pch transistors that are connected to an output terminal are controlled with the second and third potentials, and the gate terminals of the Nch transistors that are connected to the output terminal are controlled with the first and fourth potentials, such that the circuit structure can be simplified.


REFERENCES:
patent: 4713600 (1987-12-01), Tsugaru et al.
patent: 6066975 (2000-05-01), Matano
Jinzai, US patent application Publication No. US 2002/0039042, Apr. 4, 2002, Ser. No. 09/955,195 filed Sep. 19, 2001.

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