Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – For fault location
Reexamination Certificate
2001-09-14
2003-11-11
Deb, Anjan K. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
For fault location
C324S610000, C324S725000, C073S001110, C702S088000
Reexamination Certificate
active
06646446
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to resistive bridge sensors and more particularly to the detection of faults in full Wheatstone bridge type sensor elements and ASICs (application specific integrated circuits) used therewith.
BACKGROUND OF THE INVENTION
Full Wheatstone bridge sensor elements for sensing a given stimulus such as pressure, acceleration, torque or the like, coupled to ASICs for conditioning the bridge signal are known. The ability to detect sensor faults as well as faults in associated electronics and connectors is of increasing importance in high reliability applications.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and apparatus for detecting bridge faults, ASIC faults and faults external to the sensor in the connection system.
According to one preferred embodiment, two independently controlled diagnostic switches are commonly connected to one of the full Wheatstone bridge output nodes. A first diagnostic switch selectively connects a first resistor between the bridge output node and bridge supply voltage and a second diagnostic switch selectively connects a second resistor between the bridge output node and bridge ground. The first diagnostic switch closes during a first diagnostic waveform phase and opens during all other phases of operation. The second diagnostic switch closes during second and third diagnostic waveform phases and opens during all other phases of operation.
The inability to drive the conditioned output between prescribed output bounds during each phase of diagnostic waveform, e.g., lower supply voltage to upper supply voltage, at any input stimulus (e.g., pressure) level over a prescribed range, is indicative that one or more of the following fault conditions may exist:
excessive supply line resistance,
inoperative conditioning electronics,
resistive shunt across full Wheatstone bridge output nodes,
excessively resistive electrical connections between the sense element and conditioning circuit.
The first resistor value is selected to cause a differential signal across the two full Wheatstone bridge outputs minimally equal to a positive full scale stimulus signal level. The second resistor value is selected to cause a differential signal across the two full Wheatstone bridge outputs maximally equal to a negative full scale stimulus signal level. To maximize sensitivity to detect full Wheatstone bridge output shunts during the diagnostic phases, the first and second resistor values are selected to cause input signals which are both positive and negative and have a magnitude slightly more than a full scale (e.g., 105% full scale) input over the full operating temperature range. Thus, to achieve maximal benefit, the first and second resistor values are trimmed to account for tolerances in bridge resistance and minimum sensitivity over temperature and should have a value that proportionally tracks with R
brg
(T). Where R
BRG
is the effective resistance between the bridge voltage supply nodes V
BRG
and GND and is equal to (R
1
+R
2
)*R
3
+R
4
) /(R
1
+R
2
+R
3
+R
4
), ignoring the minor effects of the shunt resistor R
SHUNT
. However, such effort is not required if the resulting detection limits are acceptable. As an example, this approach has a modeled worst case detection limit of R
shunt
<0.10 R
brg
for a sense element having a factor of two variability to bridge resistance and initial sensitivity at 25 C.
To maximize sensitivity to excessive supply line resistance, the output should be driven as close to the voltage supply rails as possible. The limitations of the conditioning electronics' output drive need to be considered in this limiting case. The resistive loading can be applied to either full Wheatstone bridge output node and can either pull-up or pull-down either output. Pulling up a full Wheatstone bridge output while equivalently pulling down the other full Wheatstone bridge output can provide a simulated input which does not cause a change in the average value of the full Wheatstone bridge outputs. This form of loading may be advantageous in the presence of other fault modes sensitive to full Wheatstone bridge common mode voltage changes.
In accordance with the invention, the diagnostic waveform is used to test the major signal conditioning and fault reporting paths of the ASIC so that upon initialization assurance is provided that the electronics are in fact operating as intended, i.e., have not been damaged. The invention addresses bridge faults, ASIC faults and faults external to the sensor in the connection system. By seeing signals that are the expected signals during the sequencing of the first and second switches and the enabling of the common mode fault detection, assurance is provided that the above potential fault issues are not a problem. The expected waveform for each phase is at three defined potentials. At each phase, the system checks to see if the waveform is as expected, and, if not, a fault is indicated.
When a resistor is switched in parallel with the bridge resistors upon closing one of the switches, a greater than full scale stimulus (e.g., pressure) is simulated. When another resistor is switched in parallel with another bridge resistor, the opposite, less than lowest stimulus (e.g., zero pressure) is simulated. In a third phase, while maintaining the second switch closed, a fault condition is caused at the input nodes that allows a self test function for another fault detection circuit beyond the scope of this application. Thus, the output goes respectively to its full high range, full low range and to the range of reporting a fault, checking the major signal paths of the bridge and the ASIC.
With regard to a pressure sensor, some of the faults which can be detected include:
Phase 1, in which maximum stimulus input is simulated, is particularly sensitive to the existence of a series resistance in the power path to the sensor, connector, wire harness, contact resistance problems and ASIC damage, especially ASIC damage to the output stage.
Phase 2, in which minimum stimulus input is simulated, is sensitive to damage to the ASIC output and contact resistance in the return line.
Phase 3, in which the output is driven to a fault state near the high supply rail, is sensitive to power line resistance, output series resistance given a pull-down load resistor R
pd
shown in FIG.
1
and electrical damage to the ASIC which inhibits driving the output to the fault state.
The diagnostic procedure can be initiated each time the system applies a sufficient supply voltage to turn-on the conditioning circuit following a period with a supply voltage below the ASIC turn-off voltage threshold. Alternatively, the diagnostic procedure can be initiated periodically by the conditioning electronics.
The resistors to be switched can be scaled to obtain a controlled change in the bridge output. Thus, the magnitude of the signal being put into the rest of the ASIC can be controlled for testing of the entire electronic section as well as electrical shunts across the outputs of the bridge.
REFERENCES:
patent: 5228337 (1993-07-01), Sharpe et al.
patent: 6433554 (2002-08-01), Kawate et al.
patent: 6489787 (2002-12-01), McFadden
Sasaki et al. (“High-Precision Automated Resistance Measurement Using a Modified Wheatstone Bridge”. Precision Electromagnetic Measurements, 1988, CPEM 88 Digest. 1988, Conference on , Jun. 7-10, 1988, pp. 157-157.
Corkum David L.
Maher Thomas R.
Baumann Russell E.
Deb Anjan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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