Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2000-01-28

2003-02-18

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S202000, C257S206000, C257S208000, C257S209000, C257S210000, C257S211000, C257S259000, C257S260000, C257S390000, C257S391000, C257S758000

Reexamination Certificate

active

06522004

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device. More particularly this invention relates to a semiconductor integrated circuit device having a multi-layered wiring structure in which auxiliary signal lines are provided together with signal lines each made with polysilicon or polycide to prevent a delay in signal transmission.
BACKGROUND OF THE INVENTION
For example, a DRAM (dynamic random access memory) as one of semiconductor integrated circuit devices is configured to provide a MOS transistor and a capacitor in each of memory cells arranged in a matrix. A word line of the DRAM is formed by gate wiring of the MOS transistor, which is made of a material such as polysilicon or polycide having a comparatively large resistance. Therefore, by providing an auxiliary signal line called a backing wiring along the gate wiring, a signal can be propagated from one end of the word line to the other end thereof without development of long delays in its propagation.
FIG. 1
is a layout showing a conventional type of wiring pattern between memory cells of a DRAM having auxiliary signal lines for backing provided along lines of gate wiring. In general, each auxiliary signal line
11
is formed so as to extend along each gate wiring
12
, as shown in
FIG. 1
, in a low-resistive wired layer provided on a layer upper than the gate wiring
12
. The auxiliary signal line
11
is electrically connected to the gate wiring
12
via a contact
14
between a memory cell
13
and another memory cell
13
. In this contact
14
, a line width of the gate wiring
12
is wider than that of a wiring section other than the contact.
A wiring pitch of the auxiliary signal line
11
becomes wider by a widened line width of the gate wiring
12
in the contact
14
. The wiring pitch of the auxiliary signal line
11
matches the pitch of the gate wiring
12
, namely the pitch of the gate wiring
12
depends on the pitch of the auxiliary signal line
11
. Thus, the pitch of the gate wiring
12
may become wider than the minimum pitch of the gate wiring
12
which can originally be produced due to restriction on the process. This causes a higher degree of integration of a DRAM to be prevented. It should be noted that, in
FIG. 1
, a dotted line within the memory cell
13
represents the fact that the gate wiring
12
and auxiliary signal line
11
are electrically connected to each other inside the memory cell
13
.
To solve the above problem, there has been proposed a word line backing system that an auxiliary signal line for backing is divided into two different wired layers in upper and lower sides. Each wiring pitch of the upper and lower auxiliary signal lines is made two times wider than the pitch of the gate wiring by alternately arranging the upper and lower auxiliary signal lines for the gate wiring and making the pitch of the gate wiring narrower (e.g., Japanese Patent Laid-Open Publication No. HEI 7-45720).
According to this system, there is provided a wiring pattern that contacts each for electrically connecting the auxiliary signal line provided on the upper side to the gate wiring are arranged in a line in the vertical direction with respect to the direction to which the gate wiring extends and a lower-side linear auxiliary signal line passes through between the adjacent contacts.
Further, there has also been proposed a hierarchical word line system in which, in place of provision of the auxiliary signal line for backing, as shown in
FIG. 2
, a word line is divided into multiple sections to provide sub-word lines
15
, and a sub-low decoder
16
is provided between the memory cells
13
.
In the word line backing system disclosed in Japanese Patent Laid-Open Publication No. HEI 7-45720, however, the minimum pitch of the gate wiring actually depends on a space between a contact provided between an upper-side auxiliary signal line and gate wiring and a lower-side auxiliary signal line. Therefore, the pitch of the gate wiring can not be made narrow enough to achieve a higher degree of integration. Accordingly, there has been a problem that further higher degree of integration can not be achieved with the same semiconductor chip size or that a chip size can not be reduced with the same degree of integration.
Further, the above-described hierarchical word line system has a problem as follows. Because a plurality of sub-low decoders are distributed and arranged, the pitch of the word line can be made narrower. However, increase in the area due to provision of those sub-low decoders is larger than the case where a contact between gate wiring and the above-described auxiliary signal line for backing is provided. Resultantly, a higher degree of integration or reduction of a chip size can not be achieved.
SUMMARY OF THE INVENTION
The present invention has been made for solving the problems described above. It is an object of the present invention to provide a semiconductor integrated circuit device in which a higher degree of integration or reduction of a chip size can be achieved by providing upper and lower two-layered auxiliary signal lines in a specified wiring pattern.
In the present invention, auxiliary signal lines are provided in upper and lower layers on a signal line (gate wiring) via an insulation layer, contacts each between the signal line and the upper-side auxiliary signal line (upper-side backing wiring) are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the signal line extends, any contacts in a pair adjacent to each other among the contacts between the signal line and the upper-side auxiliary signal line are arranged on different lines, and the lower-side auxiliary signal line (lower-side backing wiring) passes through between the adjacent contacts.
With the present invention, the contacts each between the signal line and the upper-side auxiliary signal line are distributed and arranged on two columns, and also adjacent contacts in a pair are arranged on the different columns, and further the lower-side auxiliary signal line passes through between the adjacent contacts so as to weave through from one to the other. Therefore, even when a line width of the signal line is widened in the contact, the pitch of the lower-side auxiliary signal line does not need to be widened. Accordingly, wiring pitch of the upper and lower auxiliary signal lines can be made narrower, which allows a higher degree of integration of a semiconductor integrated circuit device or reduction of a chip size to be achieved.
In addition, auxiliary signal lines are provided in upper and lower layers on a signal line via an insulation layer, contacts each between the signal line and the upper-side auxiliary signal line are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the signal line extends, any adjacent contacts in a pair among the contacts each between the signal line and the upper-side auxiliary signal line may be arranged on the different lines between the lower-side auxiliary signal lines in a pair adjacent to each other.
According to one feature of the present invention, contacts each between the signal line and the upper-side auxiliary signal line are distributed and arranged on two columns, and any adjacent contacts in a pair are arranged on the different columns between adjacent lower-side auxiliary signal lines in a pair. Therefore even when a line width of the signal line is widened in the contact, the pitch of the lower-side auxiliary signal line does not need to be widened. Accordingly, wiring pitch of upper and lower auxiliary signal lines can be made narrower, which allows a higher degree of integration of a semiconductor integrated circuit device or reduction of a chip size to be achieved.
In addition, the contact consists of a conductive island formed on the same wired layer as that of a lower-side auxiliary signal line, a first auxiliary contact for electrically connecting a signal line to the island,

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