Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
2002-05-29
2003-10-14
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
Electron emitter manufacture
C438S034000, C445S049000, C445S050000, C445S051000, C313S309000
Reexamination Certificate
active
06632693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating row lines over a planarized semiconductive grid of a field emission array. Particularly, the present invention relates to row line fabrication methods that employ only two mask steps to define row lines and pixel openings therethrough.
2. Background of the Related Art
Typically, field emission displays (“FEDs”) include an array of pixels, each of which includes one or more substantially conical emitter tips. The array of pixels of a field emission display is typically referred to as a field emission array. Each of the emitter tips is electrically connected to a negative voltage source by means of a cathode conductor line, which is also typically referred to as a column line.
Another set of electrically conductive lines, which are typically referred to as row lines or as gate lines, extends over the pixels of the field emission array. Row lines typically extend across a field emission display substantially perpendicularly to the direction in which the column lines extend. Accordingly, the paths of a row line and of a column line typically cross proximate (i.e., above and below, respectively) the location of an emitter tip. The row lines of a field emission array are electrically connected to a relatively positive voltage source. Thus, as a voltage is applied across the column line and the row line, electrons are emitted by the emitter tips and accelerated through an opening in the row line.
As electrons are emitted by emitter tips and accelerate past the row line that extends over the pixel, the electrons are directed toward a corresponding pixel of a positively charged electro-luminescent panel of the field emission display, which is spaced apart from and substantially parallel to the field emission array. As electrons impact a pixel of the electro-luminescent panel, the pixel is illuminated.
An exemplary method of fabricating field emission arrays is taught in U.S. Pat. No. 5,372,973 (hereinafter “the '973 Patent”), issued to Trung T. Doan et al. on Dec. 13, 1994. The field emission array fabrication method of the '973 Patent includes an electrically conductive grid, or gate, disposed over the surface thereof and including apertures substantially above each of the emitter tips of the field emission array. Known processes, including chemical mechanical planarization (“CMP”) and a subsequent mask and etch, are employed to provide a substantially planar grid surface and to define the apertures therethrough. While the electrically conductive grid of the field emission array disclosed in the '973 Patent is fabricated from an electrically conductive material such as chromium, field emission displays that include grids of semiconductive material, such as silicon, are also known.
Typically, in fabricating row lines over planarized field emission arrays that include grids of semiconductive material, three separate mask steps and subsequent etches are employed. With reference to
FIGS. 1A and 2A
, a first mask
128
is typically required to remove semiconductive material of grid
122
from the areas between adjacent rows of emitters tips
114
and thereby define row lines
132
of the remaining portions of the semiconductive grid
122
and expose regions of dielectric layer
120
between adjacent row lines
132
.
FIGS. 1B and 2B
illustrate the use of a second mask
136
to remove conductive material
126
, which is deposited over grid
122
of semiconductive material, from the areas between adjacent row lines
132
in order to further define row lines
132
through the conductive material
126
, and from the portion of row lines
132
overlying each pixel
112
or emitter tip
114
in order to form pixel openings
140
that facilitate the travel of electrons emitted from emitter tips
114
through apertures
124
of grid
122
and past row lines
132
. With reference to
FIGS. 1C and 2C
, a third mask
150
is required to remove passivation material
134
disposed over row lines
132
from pixel openings
140
.
The use of three separate masks undesirably increases fabrication time and costs, as three separate photoresist deposition steps, three separate photoresist exposure steps, and three separate mask removal steps are required. Accordingly, row line fabrication processes that require three mask steps are somewhat inefficient.
Accordingly, there is a need for a field emission array row line fabrication method that requires fewer than three mask steps and, consequently, that increases the efficiency with which row lines are fabricated while reducing the likelihood of failure of the field emission arrays and the costs associated with fabricating field emission arrays.
SUMMARY OF THE INVENTION
The present invention includes a method of fabricating row lines on a planarized semiconductive grid of a field emission display. The row line fabrication method of the present invention employs two mask steps to define the row lines over the field emission array and to define pixel openings through the row lines.
According to the present invention, the column lines, emitter tips, overlying planarized semiconductive grid, and apertures through the semiconductive grid above the emitter tips of a field emission array may be fabricated by known processes. Each pixel of the field emission array may include one or more emitter tips, as known in the art.
A layer of conductive material may then be disposed over the substantially planar surface of the semiconductive grid of the field emission array. A layer of passivation material may then be disposed over the layer of conductive material.
In a first embodiment of the row line fabrication method of the present invention, a first mask, including a first set of apertures alignable between adjacent rows of pixels of the field emission array and a second set of apertures alignable over pixels of the field emission array, is employed to partially define the row lines of the field emission array and to define the pixel openings through the row lines. The first mask, which may be fabricated by known processes, is disposed over the layer of passivation material. Passivation material exposed through the first and second sets of apertures of the first mask is then removed by known techniques, such as etching. Next, portions of the layer of conductive material that underlie the apertures, that are substantially within a periphery of each aperture, and that are exposed through the first set of apertures and through the second set of apertures of the first mask or that are exposed through the previously etched layer of passivation material are removed, such as by known etching techniques.
Another, second mask is employed to further define the row lines and includes apertures alignable between adjacent rows of pixels of the field emission array. The second mask may be fabricated and disposed over the field emission array as known in the art. Material may be removed from the semiconductive grid through the apertures of the second mask, for example, by known etching techniques, to define the row lines.
In an alternative embodiment of the row line fabrication method of the present invention, the first mask may only include apertures alignable between adjacent rows of pixels of the field emission array. The apertures of the first mask facilitate removal of underlying passivation material, conductive material, and semiconductive material substantially within the peripheries of the apertures, such as by known etching techniques for each of these materials. The second mask includes apertures alignable over pixels of the field emission array. The passivation material underlying and substantially within the peripheries of each of the apertures of the second mask and exposed through the apertures of the second mask may be removed by known techniques, such as by etching. The conductive material that is then exposed through the apertures of the second mask or through the regions of the overlying layer of passivation material from which passivation materi
Micro)n Technology, Inc.
TraskBritt
Zarneke David A.
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