Offset correction circuit

Details Offset correction circuit Offset correction circuit

2001-06-15

2003-06-10

Tokar, Michael (Department: 2819)

Amplifiers

With periodic switching input-output

C327S307000

Reexamination Certificate

active

06577183

ABSTRACT:

FIELD
The present invention is related to an offset correction circuit.
BACKGROUND
A signal processing system may consist of one or more stages of amplification, filtering, buffering, or other operations on a voltage waveform. The voltage waveform is usually the sum of a time-varying signal, and a constant offset voltage which contains no information and may interfere with the processing of the voltage waveform. For example, the offset voltage may limit the amount of amplification that can be applied to the voltage waveform.
An offset correction loop can be used to remove a fixed offset or a slowly-varying offset.
FIG. 1
shows a typical offset correction loop. The input voltage
100
is the sum of an offset voltage and a signal voltage. A clamp circuit
106
generates an estimate of the offset voltage which is subtracted from the input voltage
100
by a summer
110
. The offset voltage estimate is updated based on the difference between the output voltage
102
and the reference voltage
104
during offset calibrate intervals, during which the signal voltage is known to be zero.
For example, if the output voltage
102
is higher than the reference voltage
104
during an offset calibrate interval, the clamp
106
will increase the input offset estimate. If the output voltage
102
is lower than the reference voltage
104
during the offset calibrate interval, then the input offset estimate that is subtracted from the input voltage
100
is decreased. The loop settles when the output voltage
102
equals the reference voltage
104
during the offset calibrate intervals.
Normally, circuits not only take offset voltages from input signal waveforms but also have internal offsets which create offset voltages at their outputs. For example, to remove the offset of an amplifier, one could use an offset correction loop prior to the amplifier to keep it from saturating as a result of input offset voltage, and another offset correction loop after the amplifier to remove any offset voltage produced by the amplifier itself. The offset correction loop of
FIG. 1
can be used for both purposes.
In
FIG. 2
, a offset correction circuit
200
is located between the output of the first summer
110
and the output voltage
102
. The advantage of this architecture is that a single offset correction loop can be used to remove offsets in both the input waveform and the added circuit.
SUMMARY
The present invention is directed to an offset correction circuit comprising a first summing unit, a second summing unit, a differential transconductance amplifier, and a capacitor. The differential transconductance amplifier is located between the output of the second summing unit and the second input of the first summing unit; the capacitor located between the second input of the first summing unit and a first reference voltage. The offset correction circuit input may be located before the first input of the first summing unit and the offset correction circuit output may be located between the output of the first summing unit and the first input of the second summing unit. In other embodiments, the differential transconductance amplifier may be implemented with fully differential output and may use variable resistors. The variable resistors may be implemented with NMOS devices. In another embodiment the differential transconductance amplifier is nonlinear.
In an embodiment of the invention a separate circuit is located between the output of the first summing unit and the circuit output. In another embodiment a switch is located between an output of variable gain amplifier and the capacitor. A second reference voltage may be coupled to the second input of the second summing unit. In a further embodiment a lowpass filter is located between the output of the second summing unit and an input of the voltage integrator. The lowpass filter may be an R-C filter employing a switched-capacitor resistor.
A further embodiment of the invention is directed to a method of correcting a circuit offset, the method comprising the steps of: providing a voltage integrator, comprising an transconductance amplifier and a capacitor, between a circuit input and a circuit output; calibrating the voltage integrator by storing an input offset voltage on the capacitor; and subtracting the input offset voltage estimate from an input waveform.
A further embodiment of the invention is directed to an offset correction loop comprising a transconductance amplifier connected between a circuit input and a circuit output, a capacitor connected between a circuit input and a reference voltage, and a switch controlled by an offset calibrate signal.


REFERENCES:
patent: 4050030 (1977-09-01), Russell
patent: 5392001 (1995-02-01), Uhling et al.
patent: 5508656 (1996-04-01), Jaffard et al.
patent: 5648738 (1997-07-01), Welland et al.
patent: 5844439 (1998-12-01), Zortea
patent: 6005431 (1999-12-01), Mehr et al.
patent: 6288604 (2001-09-01), Shih et al.
patent: 6300824 (2001-10-01), Moughabghab
patent: 6317064 (2001-11-01), Ferrer et al.
patent: 6356217 (2002-03-01), Tilley et al.

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