Track and hold circuit

Details Track and hold circuit Track and hold circuit

2000-10-05

2003-06-10

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S091000

Reexamination Certificate

active

06577168

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a track and hold circuit, and more particularly to a highly accurate, low-distortion track and hold circuit for use in a front end of an analog-to-digital converter.
2. Description of the Related Art
A track and hold circuit is one of basic analog circuits for use at the front end of an analog-to-digital converter, and serves to sample the value of a signal that changes continuously with time, at discrete time intervals. The track and hold circuit causes signal distortion for three reasons, which will be described below using a most fundamental conventional track and hold circuit shown in
FIG. 3
of the accompanying drawings.
(A) Variation of Time Required for Charging a Holding Capacitor in a Track Mode:
The illustrated track and hold circuit shown in
FIG. 3
comprises two amplifiers
101
,
102
, a MOS transistor
103
operable as an FET switch, a holding capacitor
104
, and a clock source
105
. The MOS transistor
103
has a bulk terminal connected to a common potential point (ground). When the MOS transistor
103
is turned on, a base resistance R
on
depends on a block voltage, i.e., a gate drive voltage V
&PHgr;
of the MOS transistor
103
, an input voltage V
in
applied to the drain thereof, and a threshold voltage V
th
, and is related to these parameters as follows:
R
on
=1/{&bgr;(
V
&PHgr;
−V
in
−V
th
)}  (1)
Where &bgr; represents a constant determined by the fabrication process and is expressed by &bgr;=&mgr;C
ox
W/L (&mgr;: mobility, C
ox
: gate oxide film capacitance, W: gate width, L: gate length).
Therefore, when the input voltage V
in
varies, the base resistance R
on
also varies, and hence the time constant for time required for charging the holding capacitor
104
, which is given by R
on
×C
H
(C
H
is the capacitance of the holding capacitor
104
). The signal dependency of the base resistance R
on
of the MOS transistor
103
which depends on the input voltage V
in
that is supposed to vary, causes time for charging the holding capacitor
104
to vary, resulting in harmonic distortion.
(B) Variation of Timing Upon Mode Transition:
When the input voltage V
in
varies, the timing of transition from the track mode to a hold mode varies as shown in
FIG. 4
of the accompanying drawings. Specifically, the voltages need to satisfy the condition V
&PHgr;
≧V
in
+V
th
upon transition from the track mode to the hold mode, and need to satisfy the condition V
&PHgr;
≦V
in
+V
th
upon transition from the hold mode to the track mode. Therefore, if the input voltage V
in
is large, the timing of transition from the track mode to the hold mode is delayed, and the timing of transition from the hold mode to the track mode is advanced. Conversely, if the input voltage V
in
is small, the timing of transition from the track mode to the hold mode is advanced, and the timing of transition from the hold mode to the track mode is delayed. The signal-dependent timing variation also tends to result in harmonic distortions.
(C) Charge Injection Upon Mode Transition:
As shown in
FIG. 5
of the accompanying drawings, when the track mode changes to the hold mode, charges stored under the gate of the MOS transistor
103
are discharged. Specifically, charge Q
1
injected into the gate when the MOS transistor
103
is turned on is discharged when the MOS transistor
103
is turned off. Furthermore, charge Q
2
stored in a parasitic capacitance C
gs
between the gate and source of the MOS transistor
103
when the MOS transistor
103
is turned on is discharged when the MOS transistor
103
is turned off. When the MOS transistor
103
is turned off, these charges Q
1
, Q
2
flow into the holding capacitor, possibly causing harmonic distortion. It is known that the charges Q
1
, Q
2
are determined according to the following equations:
Q
1
=−
C
ox
A
(
V
&PHgr;−
V
in
−V
th
)  (2)
where C
ox
represents the gate oxide film capacitance per unit area of the MOS transistor
103
, A represents the gate area of the MOS transistor
103
, V
&PHgr;
represents the clock voltage, V
in
represents the input voltage V
in
applied to the drain of the MOS transistor
103
, and V
th
represents the threshold voltage.
Q
2
=−
C
gs
(
V
in
+V
th
)  (3)
where C
gs
represents the gate-to-source capacitance of the MOS transistor
103
, and V
th
represents the threshold voltage. The gate-to-source capacitance C
gs
depends on the input voltage V
in
as expressed by the following equation:
C
gs
=C
gs0
/{1−(
V
&PHgr;−
V
in
−V
th
)&psgr;
0
}
½
  (4)
where
&psgr;0
represents a built-in potential, and C
gs0
represents the value of the gate-to-source capacitance when V
gs
=0.
As described above, both the charges Q
1
, Q
2
depend on the input voltage V
in
, and are responsible for harmonic distortion. Particularly, the charge Q
2
depends nonlinearly on the input voltage V
in
.
Attempts have been made to reduce distortion caused by variations in the input voltage. According to one effort, the gate drive voltage is increased to reduce the dependency of the on resistance upon the input signal, and the MOS transistor is arranged as a CMOS switch to reduce the on resistance. These proposals require a necessary drive voltage to be increased, as is apparent from the characteristics of the MOS transistor, and an increased drive voltage goes against the recent tendency toward lower voltages for circuit design, and results in a large feedthrough of charges. In addition, a high-speed PMOS is needed, and the problem of timing deviations due to variations in the threshold voltage V
th
remains unsolved. Accordingly, the above proposals have proven unsatisfactory.
An effort has also been made to change the gate voltage depending on the level of the input signal. Examples of such an effort are described in Application Note, dated Mar. 10, 1997, relating to AN301, of Siliconix division of TEMIC Semiconductors, and Japanese Patent No. 2833070 (Japanese Patent Laid-open No. Heisei 3-219724). However, these circuit arrangements require a voltage source ranging from 10 to 15 volts, and do not lend themselves to a system LSI device which needs a lower operational voltage, though they can be used for measuring instruments. In addition, the circuit arrangements have a complex driver circuit.
It has also been proposed to use a dummy switch to reduce the charge injection. For example, reference should be made to Japanese Patent Laid-open No. Heisei 10-312698. According to the proposed scheme, another MOS transistor is inserted between the MOS transistor
103
and the amplifier
101
at the output stage or ground, for absorbing at least part of the charge flowing into the holding capacitor. One problem with the proposal is that the timing to drive the added MOS transistor needs to be controlled finely, and a more essential problem is that it is difficult to handle the charge injection quantitatively.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a track and hold circuit which can operate at a lower voltage and can reduce distortions in waveforms that are held by the circuit.
According to the present invention, the signal distortion of a track and hold circuit is lowered by controlling a bulk potential or substrate potential of a MOS transistor switch.
According to the present invention, there is provided a track and hold circuit which includes a MOS transistor switch and a holding capacitor, the arrangement being such that a bulk potential of the MOS transistor switch is changed in phase with an input signal.
According to the present invention, there is also provided a track and hold circuit which includes a MOS transistor switch for selectively transmitting and blocking an input voltage depending on a gate voltage thereof, a holding capacitor electrically connected to the MOS transistor switch, for generating an outp

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