Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-02-05
2003-06-24
Nguyen, Chanh (Department: 2675)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S099000, C345S213000
Reexamination Certificate
active
06583785
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 90100699, filed Jan. 12, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a display device and corresponding method of operating the display device. More particularly, the present invention relates to a display device whose clock rate can be adjusted according to the actual operating state so that power consumption is reduced.
2. Description of Related Art
Due to the rapid development in Internet technologies, computer use is becoming more and more popular. The type of data that are shuttled between users includes document data as well as voice and image data. With so much information transferred through various media, transmission rates and processing efficiency have become important aspects of computer system research. Amongst the various types of transmissions, image data transmission normally requires the largest data volume. Image data are normally displayed on a display device (for example, a liquid crystal display (LCD) or a cathode ray tube (CRT)). In general, the display controller of a display device has a pixel clock pulsing at a fixed frequency. Image signals are displayed on a screen according to a fixed clock rate.
In practice, image signals need not be displayed using the same clock rate at all times. For example, a user may have to go over many scenes in succession at the beginning and hence a rapid switching of images is desirable. If the clock rate is too low, the user may have to wait a long time. On the contrary, once a user has stepped into a special program execution, identical scenes or scenes with little variation are often displayed. Under such circumstances, power consumed by the display controller and any associated external memory is wasted if a high clock rate is maintained. Therefore, not only is the cost of operation high, but the working life of the equipment is also shortened.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a variable clock rate display device and corresponding method of operating the device. The device is capable of finding an optimal clock frequency according to the actual state of the computer system so that the user's demands are met while power consumption is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a variable clock rate display device. The display device includes a decision block, a frequency change block, a first multiplexer, a second multiplexer, a memory unit, a memory controller, a display controller and a display panel.
The decision block receives a CPU write address signal, an on-screen start address signal and an on-screen end address signal to determine if a CPU update on-screen mean data and a change on-screen mean area need to be transferred to the frequency change block. The frequency change block receives the CPU update on-screen mean data and a change on-screen mean area, together with a synchronous signal for submitting a clock set signal. The first multiplexer receives the clock set signal to determine a pixel clock signal and then outputs a corresponding clock set signal. The second multiplexer receives the corresponding clock set signal to determine a memory read clock signal. The memory unit holds a piece of data. The memory controller receives the memory read clock signal and retrieves the data from the memory unit. The memory controller then outputs a memory read data clock pulse. The display controller receives the memory read data clock pulse and the pixel clock signal to output an on-screen data signal and a corresponding pixel clock signal. The display panel receives the on-screen data signal and the corresponding pixel clock signal to produce an image. The display panel can be a liquid crystal display (LCD) or a cathode ray tube (CRT), for example.
This invention also provides a method of adjusting the clock rate of a display device. First, a pixel clock and a memory read clock are set to the largest values when the display device is initialized. If the CPU reads from the memory area, the frequency of the pixel clock and the memory read clock is adjusted according to the frequency of the CPU update on-screen memory and the variation of the CPU change on-screen memory block. On the other hand, if the CPU does not initiate any updating, the pixel clock and the memory read clock are tuned down to their minimum values.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5745106 (1998-04-01), Chandavarkar
patent: 5796391 (1998-08-01), Chiu et al.
patent: 6020904 (2000-02-01), Clark
Integrated Technology Express Inc.
Nguyen Chanh
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