Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2000-08-02
2003-08-19
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S121000, C438S122000, C438S125000, C438S126000
Reexamination Certificate
active
06607943
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor package and more particularly to a low cost cavity type ball grid array (BGA) semiconductor package with a very low profile and to a method for its fabrication.
BACKGROUND OF THE INVENTION
Semiconductor devices are widely used in various types of electronic products, consumer products, printed circuit cards, and the like. In an integrated circuit, a number of active semiconductor devices are formed on a chip of silicon and interconnected in place by leads to form a complete circuit. The size and cost of the semiconductor devices are important features in many of these applications. Any reduction in the cost of producing the package or reduction in the size or thickness of the package can provide a significant commercial advantage.
Ball grid array semiconductor packages are well known in the electronics industry. Currently available prior types include the Plastic Ball Grid Array (PGBA), the Ceramic Ball Grid Array (CBGA), and the Tape Ball Grid Array (TBGA). A BGA package typically comprises a substrate, such as a printed circuit board, with a series of metal traces on the top side. This series of metal traces is connected to a second series of metal traces on the bottom side of the substrate through a series of wire channels located around the periphery of the substrate. A semiconductor die, having a plurality of bond pads, each associated with an input or output of the semiconductor die, is mounted to the top side of the substrate. The bond pads are connected to the series of metal traces on the top side of the substrate by wire bonds. Typically, the semiconductor die and wire bonds are encapsulated with a molding compound. The second series of metal traces located on the bottom side of the substrate each terminate with a contact pad where a conductive solder ball is attached. The conductive solder balls are arranged in an array pattern, and are connected to the next level assembly or a printed wiring board in the final application.
Alternatively, the substrate may be provided with a series of metal traces on only the bottom side, and the semiconductor die is attached to the bottom of the substrate. The bond pads of the semiconductor die are attached to the series of metal traces on the bottom side of the substrate. The series of metal traces located on the bottom side of the substrate terminate with a contact pad where a conductive solder ball is attached. The conductive solder balls are arranged in an array pattern, and are connected to the next level assembly or a printed wiring board in the final application.
FIG. 1A
illustrates a cross-sectional view of a typical prior art perimeter BGA integrated circuit package
10
. BGA package
10
comprises a substrate
11
having top conductive traces
12
formed on an upper surface of substrate
11
. Substrate
11
typically is formed from an organic epoxy-glass resin based material, such as bismaleimide-triazin (BT) resin or FR-4 board. The thickness of substrate
11
is generally on the order of 0.35 mm. Bottom conductive traces
13
are formed on a lower surface of substrate
11
and are electrically connected to top conductive traces
12
through vias or plated through-holes
14
. Vias
14
extend from the upper surface of substrate
11
to the lower surface. Vias
14
contain a conductive material such as copper. Top conductive traces
12
terminate with bond posts or pads
21
. Bottom conductive traces
13
terminate with ball or terminal pads
16
. Top conductive traces
12
, bottom conductive traces
13
, ball pads
16
, and bond posts
21
comprise an electrically conductive material such as copper or copper plated with gold. Not all top conductive traces
12
, bottom conductive traces
13
, and vias
14
are shown to avoid overcrowding of the drawing.
BGA package
10
further comprises a semiconductor element or semiconductor die
18
attached to a die attach pad
23
on the upper surface of substrate
11
. Semiconductor die
18
is attached to die attach pad
23
using an epoxy. Semiconductor die
18
has a plurality of bonding or bond pads
22
formed on an upper surface. Each of the plurality of bond pads
22
is electrically connected to top conductive traces
12
with a wire bond
19
. Typically, semiconductor die
18
, wire bonds
19
, and a portion of substrate
11
are covered by an encapsulating enclosure
24
, such as an epoxy enclosure.
Conductive solder balls
26
are each attached to a ball pad
16
. Conductive solder balls
26
are metallurgically wetted to ball pads
16
during a reflow process. The inner-most conductive solder balls
26
are typically underneath or adjacent to semiconductor die
18
. Conductive solder balls
26
are later connected to a next level of assembly or printed circuit board
28
using a standard reflow process. Conductive solder balls
26
connect to contact pads
29
to form solder joints
25
. After the mounting process, solder joints
25
take a flattened spherical shape defined by solder volume and wetting areas. The number and arrangement of conductive solder balls
26
on the lower surface of substrate
11
depends on circuit requirements including input/output (I/O), power and ground connections.
FIG. 1B
illustrates a cross-sectional view of another typical prior art perimeter BGA integrated circuit package
30
. BGA package
30
comprises a substrate
31
and a support or base substrate
32
attached to substrate
31
. Substrate
31
and support substrate
32
typically are formed from an organic epoxy-glass resin based material, such as bismaleimide-triazin (BT) resin or FR-4 board. The thickness of substrate
31
and support substrate
32
is generally on the order of 0.35 mm each. Substrate
31
has an opening or aperture
33
, which forms a cavity with support substrate
32
as the lower cavity surface. The dimensions (length and width) of support substrate
32
are greater than the dimensions of opening
33
and less than the dimensions of substrate
31
. Substrate
31
has top conductive traces
34
formed on the upper surface, and bottom conductive traces
35
formed on the lower surface electrically connected to top conductive traces
34
through vias or plated through holes
36
. Top conductive traces
34
terminate at one end with a bond post or pad
38
. Bottom conductive traces
35
terminate with a conductive ball pad or contact
39
. A plurality of conductive solder balls or contacts
40
are each coupled to a conductive ball pad
39
.
BGA package
30
also contains a semiconductor element or semiconductor die
48
attached to a die attach pad
43
on the upper surface of support substrate
32
. Support substrate
32
and opening
33
provide a cavity for semiconductor die
48
, which minimizes the effect of die thickness on the overall package height. Bond pads
42
are electrically connected to top conductive traces
34
with a wire bond
49
. Typically, semiconductor die
48
, wire bonds
49
and a portion of substrate
31
are covered by an encapsulating enclosure
50
, such as an epoxy enclosure. Conductive solder balls
40
are later connected to a next level of assembly or a printed circuit board
52
using a standard reflow process.
BGA packages
10
,
30
have several disadvantages, including a high profile. Height
17
of BGA package
10
is typically on the order of 2.4 mm, while height
54
of BGA package
30
is typically on the order of 0.9 to 1.46 mm. It is often desirable to minimize the thickness of a packaged semiconductor device since they are widely used in various types of electronic products, portable consumer products, telephones, pagers, automobiles, integrated circuit cards, and the like, in order to make the final products as thin as possible. Thus, there exists a need in the electronics industry for a BGA package that has a very low profile.
Another disadvantage of BGA packages
10
,
30
is the cost of production. The use of substantial amounts of substrate in the manufacturing of BGA packages increases the overall cost of production. Thus, there exists a
Dickstein , Shapiro, Morin & Oshinsky, LLP
Novacek Christy
Zarabian Amir
LandOfFree
Low profile ball grid array package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low profile ball grid array package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low profile ball grid array package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3115421