Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-08-15
2003-06-24
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S117000, C257S686000
Reexamination Certificate
active
06582992
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor packaging, and specifically to a stackable semiconductor package having a chip scale outline. This invention also relates to a wafer level method for fabricating the package, and to assemblies incorporating multiple stacked packages.
BACKGROUND OF THE INVENTION
Decreases in the size of electronic devices, particularly hand held devices, has led to the development of smaller semiconductor packages. One type of semiconductor package is referred to as a chip scale package (CSP). A chip scale package includes a semiconductor die, and a lead system for transmitting signals and power to the die.
The chip scale package has a peripheral outline (footprint) that is only slightly larger than that of the die contained in the package (e.g., 1.2 times the die outline). Typically, the chip scale package includes a substrate, such as a board or a tape material, which contains the lead system for the package. The chip scale package can also include a casing configured to protect, and to insulate the die and the lead system.
The present invention is directed to a chip scale package having an outline that is the same as that of the die which it contains. The package thus possesses a true chip scale profile. In addition, the lead system for the package is formed directly on the die, without the requirement of a separate substrate.
In addition to a chip sized outline, it is advantageous for a package to be configured to facilitate assembly in electronic devices and electronic systems in dense arrays. For example, printed circuit boards, multi chip modules, and other electronic devices as well, preferably contain multiple packages in as small an area as possible. One technique for fabricating electronic devices and systems with dense arrays of packages is to stack the packages on one another to form a stacked assembly. This requires that the lead systems for all of the packages in a stacked assembly be configured for interconnection.
The present invention is directed to a chip scale package having a stackable configuration. As such, a lead system for the package permits interconnection of multiple packages to form a stacked assembly which includes any desired number of packages. Further, the package of the invention includes contacts on both major surfaces, and on the edges of the package as well, such that connections to other packages, or to other electronic elements of a electronic device or system is facilitated.
Another consideration in the design of chip scale packages is the method for fabricating the packages. The chip scale package of the present invention can be fabricated using a wafer level fabrication method that is simple, reliable and capable of volume manufacture using conventional equipment.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved stackable semiconductor package, a method for fabricating the package, and a stacked assembly that includes multiple stacked packages are provided.
The package includes a semiconductor die containing integrated circuits in a desired configuration (e.g., DRAM, SRAM etc.). The package has peripheral edges, and a peripheral outline (footprint) that correspond to the edges and the outline of the die. In addition, the package has a circuit side (first side) and a back side (second side) that correspond to the circuit side and the back side of the die.
In addition to the die, the package includes circuit side stacking pads, and circuit side conductors in electrical communication with the integrated circuits on the die. The package also includes back side stacking pads on the back side, and back side conductors on the back side in electrical communication with the circuit side conductors. In addition, the package includes conductive grooves (castellations) in one or more edges thereof, configured as interlevel conductors between the circuit side and the back side of the package. The plated grooves can also function as edge contacts for interconnecting multiple packages in a stacked assembly, or for electrically connecting the package, or the stacked assembly, to a supporting substrate, such as a circuit board.
The package also includes stacking contacts, such as bumps or balls, formed on the circuit side stacking pads, or alternately on the back side stacking pads. The stacking contacts are configured for mating engagement with the stacking pads on an adjacent stacked package. The stacking contacts permit multiple packages to be stacked to one another, with the stacking contacts and the stacking pads on adjacent packages bonded to one another. In addition, the package can include external contacts on the back side, such as bumps or balls, configured to physically and electrically attach the package, or a stacked assembly, to a supporting substrate.
The method for fabricating the package includes the initial step of providing a substrate, such as a wafer or portion thereof, which contains multiple semiconductor dice separated by spaces. The spaces can be configured as streets for saw cutting, or otherwise singulating, the dice from the substrate into separate packages. The method also includes the steps of forming circuit side conductors, and circuit side stacking pads, on the dice contained on the substrate. The circuit side conductors, and the circuit side stacking pads, can be formed by deposition and etching of a metal redistribution layer. In addition, the method includes the step of forming back side conductors, and back side stacking pads, on the dice contained on the substrate. The back side conductors, and the back side stacking pads, can also be formed by deposition and etching of a metal redistribution layer.
The method also includes the step of forming conductive vias in the substrate in the spaces between the dice. The conductive vias can be formed by etching openings in the substrate, insulating the openings, and then covering the walls of the openings (or completely filling the openings) with a conductive material, such as a metal or a conductive polymer. The conductive vias are configured such that during a singulation step, the dice are singulated into separate packages, and separate portions of the conductive vias remain with different packages. The separate portions of the conductive vias form the conductive grooves in the edges of the packages.
The method also includes the steps of forming the stacking contacts on the stacking pads, and if required, forming the external contacts on the back side. Prior to the singulation step, two or more substrates can be stacked to one another, and the stacking contacts on a first substrate bonded to the stacking pads on an adjacent second substrate. The singulation step can thus be used to form stacked assemblies that contain any desired number of stacked packages.
REFERENCES:
patent: 4505799 (1985-03-01), Baxter
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5063177 (1991-11-01), Geller et al.
patent: 5107328 (1992-04-01), Kinsman
patent: 5138434 (1992-08-01), Wood et al.
patent: 5155067 (1992-10-01), Wood et al.
patent: 5229647 (1993-07-01), Gnadinger
patent: 5266912 (1993-11-01), Kledzik
patent: 5334857 (1994-08-01), Mennitt et al.
patent: 5384689 (1995-01-01), Shen
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5444296 (1995-08-01), Kaul et al.
patent: 5468999 (1995-11-01), Lin et al.
patent: 5474957 (1995-12-01), Urushima
patent: 5562971 (1996-10-01), Tsuru et al.
patent: 5633530 (1997-05-01), Hsu
patent: 5646828 (1997-07-01), Degani et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 5677566 (1997-10-01), King et al.
patent: 5689091 (1997-11-01), Hamzehdoost et al.
patent: 5696033 (1997-12-01), Kinsman
patent: 5723900 (1998-03-01), Kojima et al.
patent: 5723901 (1998-03-01), Katsumata
patent: 5739585 (1998-04-01), Akram et al.
patent: 5753857 (1998-05-01), Choi
patent: 5763939 (1998-06-01), Yamashita
patent: 5789803 (1998-08-01), Kinsman
patent: 5796038 (1998-08-01), Manteghi
patent: 5811879 (1998-09-01), Akram
patent: 5995379 (1999-11-01), Kyougoku et al.
pate
Jeung Boon Suan
Kwang Chua Swee
Loo Neo Yong
Poo Chia Yong
Waf Low Siu
Gratton Stephen A.
Nguyen Thinh
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