Grounded fill in a large scale integrated circuit

Details Grounded fill in a large scale integrated circuit Grounded fill in a large scale integrated circuit

2000-05-25

2003-08-19

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S207000, C257S758000

Reexamination Certificate

active

06608335

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to integrated circuits having grounded fill elements.
2. Background
Large scale central processing unit (CPU) integrated circuit computer chips increasingly contain more transistors and more metal layers. At the same time, the feature size of wires and other chip components is getting smaller as the enabling technologies improve. Because of increased chip complexity, chip designers and manufacturers are encountering challenges that they did not have to address in the design and manufacture of less complex chips.
FIG. 1
is a cross-section diagram showing an integrated circuit chip having seven metal layers in accordance with the prior art (not to scale). The chip includes a wafer (
10
). A dielectric layer (
12
) is formed on the wafer. The first metal layer, or metal
1
(
14
) is deposited next. Metal
2
(
18
), metal
3
(
20
), metal
4
(
22
), metal
5
(
24
), metal
6
(
26
) and metal
7
(
28
) are successively deposited. Dielectric layers (
16
,
30
,
32
,
34
,
36
,
38
,
40
) separate the metals. The chips are grown from the wafer on up. Therefore, for example, it can be said that metal
4
(
22
) is the upper adjacent layer to metal
3
(
20
) and that metal
2
(
18
) is the lower adjacent layer to metal
3
(
20
). Each metal layer contains etched wires including conductors (at V
dd
) and ground wires (at V
ss
). Generally, the metal layers are thicker at the top of the chip.
Integrated circuit chips require multilayer interconnects to connect various transistors to complete a circuit. In the metal layers of an IC chip, there are some areas with high interconnect density and others with low density. Due to this variation in density, the dielectric layer in aluminum and the copper layer in a copper interconnect scheme can be excessively polished in low density areas during the chemical mechanical polishing (CMP) process. In order to avoid this issue, dummy metal is inserted in the design to make the interconnect density in a layer uniform.
When dummy metal is included in a chip design without further consideration, it will be electrically floating and will capacitively couple with the signal lines above and below. It would therefore be desirable to connect dummy metal to ground, thereby avoiding unwanted noise in the chip.
Computer Aided Design (CAD) is used extensively in the design of computer chips. Many CAD tools are commercially available. However, commercially available CAD tools suffer from limitations of memory and processing speed, so that optimal design of grounded fills in a chip is not possible by merely using off-the-shelf CAD tools.
It is therefore desirable to improve on existing CAD tools to allow for better design of grounded fills within a large scale integrated circuit chip. Such improved CAD tools and systems result in integrated circuits not achievable using previous technologies.
BRIEF DESCRIPTION OF THE INVENTION
An integrated circuit has a plurality of metal layers separated by a plurality of insulating layers. The integrated circuit comprises a pair of conductors on a first metal layer; at least one conductive fill element disposed between the conductors; and a via connecting the fill element to a ground contact on a metal layer adjacent to said first metal layer, where the via is formed of a conductive material.


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patent: 4962058 (1990-10-01), Cronin et al.
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patent: 5986294 (1999-11-01), Miki et al.
patent: 6175145 (2001-01-01), Lee et al.
patent: 2002/0084526 (2002-07-01), Kasai
Stine, et al., “The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes”, Mar. 1998, IEEE Transactions on Electron Devices, vol. 45, No. 3, pp. 665-679.

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