Pulse or digital communications – Synchronizers – Self-synchronizing signal
Reexamination Certificate
1998-12-29
2003-04-15
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Self-synchronizing signal
C375S355000
Reexamination Certificate
active
06549595
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a serial communication system comprising at least one transmitter circuit and at least one receiver circuit interconnected via a communication medium; the communication medium providing at least a first and a second parallel signal carrier for transporting a respective first and second signal from the transmitter circuit to the receiver circuit;
the transmitter circuit comprising means to, in synchronization with a clock signal, serially represent a combination of the clock signal and data item(s) of a data message as the first and second signal such that at a data item boundary a signal transition occurs of either the first or the second signal; and
the receiver circuit comprising means to recover the clock signal by detecting and combining signal transitions of the first and second signal and to recover the data message from the first and/or the second signal.
The invention further relates to a transmitter apparatus and receiver apparatus for use in such a system.
The invention also relates to a method of serially communicating between at least one transmitter circuit and at least one receiver circuit interconnected via a communication medium; the communication medium providing at least a first and a second parallel signal carrier for transporting a respective first and second signal from the transmitter circuit to the receiver circuit; the method comprises:
in synchronization with a clock signal, serially encoding a combination of the clock signal and data items(s) of a data message as the first and second signal such that at a data item boundary a signal transition occurs in either the first or the second signal;
outputting the first and second signal from the transmitter circuit via the respective signal carriers;
inputting the first and second signals from the respective signal carriers into the receiver circuit; and
decoding the first and second signals to recover the clock signal by detecting and combining signal transitions of the first and second signal; and recovering the data message from the first and/or the second signal.
Such a serial communication system and method are known from U.S. Pat. No. 5,341,371. This system discloses a high-speed communication interface connecting a transmitter and a receiver circuit via two parallel signals, referred to as the data signal and strobe signal respectively. Under control of a clock, data bits of a data message are output serially. The data bit is presented in a conventional binary form, where a zero data bit is transmitted as a low signal level and a one data bit as a high signal level. A transition occurs in the data signal only when the data changes. A half-period clock signal is used of which both edges of the clock signal are used. The half-period clock signal is represented in the strobe signal. The transmitter only effects a signal transition on the strobe signal when there is no transition on the data signal. The receiver recovers the clock signal by combining transition information from both the strobe signal and the data signal. The receiver retrieves the data bits by sampling the data signal under control of the recovered clock.
The known system discloses a higher-level communication protocol, where information is transferred via the bus in the form of tokens. A token starts with a parity bit, followed by a bit indicating whether the token carries a data byte or is used for control purposes. Consequently, a data byte is transferred using a ten-bit token. The system allows transfer of variable length messages, where a message consists of one or more bytes. An N-byte message is sent as a succession of N tokens each carrying a data byte. To indicate the end of a message, a special end-of-packet or end-of-message token of three bits is sent.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an alternative low-cost, high-speed communication system, transmitter and receiver apparatus for use in such a system, and communication method.
To meet the object of the invention, the transmitter circuit is operative to cause a transition of the first signal at a data item boundary preceding data item d of the data message if a function f(d) of the data item d has a first value and to cause a transition of the second signal at the data item boundary if the function f(d) has a different second value. In this way a system is achieved, where both signals are used in a similar and complementary way to represent f(d), enhancing the symmetry of the system. The binary value of f(d) determines in which signal a transition occurs. Recovery of the clock is possible since during the transfer of a data message at each data bit boundary always one of the signals changes level. The recovery may, for instance, be based on a simple XOR operation. During the transfer of a data message both signals on average change level at half the nominal clock frequency (transitions occur only at data bit boundaries), ensuring a low frequency signal. During the transfer of a data message it is avoided that both signals change level at a data bit boundary.
The value of the function f(d) may simply be the data bit itself (f(d)=d), requiring no additional logic for encoding/decoding the data bit. Alternatively, simple binary logic may be used which does not negatively affect the bit-rate of the system. As an example, f(d) may be a binary combination, such as XOR, of the data bit d with at least one bit of a predetermined codeword. The codeword may, for instance, be used to increase security of the system. For more secure systems, the function f(d) may be based on more advanced cryptographic principles such as a stream cipher. This may, however, affect the bit-rate.
In a preferred embodiment, the receiver determines the value of f(d) by detecting whether a transition occurred in the first or second signal. To this end, the receiver may comprise means for detecting a rising/falling edge in one or both signals. If at a moment that substantially coincides with a data bit boundary, as indicated by the recovered clock, no edge is detected in one of the signals this can be seen as implying that the edge must have occurred in the other signal. As such the symmetry of the system makes it sufficient to detect whether a transition occurred in only one of the signals.
In a further embodiment, the recovered clock signal is used to sample the signal in a reliable and simple way. The stable signal level of two successive samples is compared to determine in a simple way whether a transition has occurred or not.
In a further embodiment, error detection is performed by recovering the data from both signals and comparing the outcome. In this way certain transmission errors, such as one-bit errors, can be detected without using a parity bit. This simplifies the protocol and saves a bit location on the bus compared to the prior art system.
In a further embodiment, it is determined whether a transition occurred by comparing successive samples after converting the serial stream of samples to a parallel word. In this way the comparison is less time-critical and can be performed at a lower frequency.
In a further embodiment, the system is made highly suitable for transferring a stream of data messages (also referred to as words), such as for instance is the case for transferring audio or video data. The system is capable of transferring such data in a synchronous manner, with a simple detection of the end of a word. Lack of one or more transitions in the signal is used to indicate the boundary (beginning/end) of a word. In principle, such a detection can already be performed after a duration of little more than one data bit period following the last transition. Moreover, a ‘gap’ in the transitions can be generated and detected in a very simple manner. This compares favorably with the system of U.S. Pat. No. 5,342,371, where a special 3-bit token needs to be generated and detected. Furthermore, the system according to the invention allows variable word lengths at bit boundaries and is not restricted to word-
Den Besten Gerrit W.
Pelgrom Marcellinus J. M.
Biren Steven R.
Chin Stephen
Koninklijke Philips Electronics , N.V.
Lugo David B.
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