Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-11-21
2003-10-07
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S075000, C216S078000, C216S088000, C438S720000, C438S745000, C438S754000
Reexamination Certificate
active
06630402
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductors, and more particularly to integrated circuits that are resistant to the formation of cracks in a passivation layer formed over an interconnect metal layer by producing an interconnect metal layer having a configuration with rounded comers that are believed to reduce the stress transferred to the passivation layer ultimately formed thereon.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, an integrated circuit (IC) device is formed over a semiconductor substrate. The IC device usually includes, for example, transistors and/or capacitors, which are interconnected by an interconnect metal layer. After the structure of the IC device is formed, a passivation layer is then formed over the IC structure so as to protect the IC device from external damage. In order to effectively protect the IC structure, the passivation layer must be uniformly deposited, have no voids and sufficient hardness, and be able to resist cracking, penetration of water vapor or alkaline ions, and mechanical damage.
Some common materials for forming the passivation layer include silicon nitride and phosphosilicate glass (PSG). Silicon nitride has a high density and good hardness characteristics such that it can effectively resist the penetration of water vapor or alkaline ions and resist mechanical damage. PSG includes phosphoric atoms, which have a gettering property so that the water vapor and alkaline ions are effectively absorbed by it. The effectiveness of these protections prolongs the life of IC devices protected with passivation layers.
Conventional metal patterning methods, including reactive ion etching (RIE) and damascene techniques, employ anisotropic etching processes which can produce features with dimensions that are on the order of half a micron in size or less. In practice, however, anisotropic etching typically results in the creation of sharp corners in the metallized features so formed, which tend to cause high stresses in surrounding dielectric layers. In particular, these high stresses have been found to cause cracks in an overlying passivation layer. These high stresses have also been found to cause “cratering” in the fuses which are formed on integrated circuits for various purposes.
In an effort to reduce stress-induced cracking, increasing the thickness of a protective passivation layer has been suggested. However, the beneficial effects of this suggestion are limited by a corresponding increase in the brittleness of a thicker layer.
U.S. Pat. Nos. 5,416,048, 4,425,183 and 4,352,724 each suggest rounding of top corners, as seen from a sectional view, of an interconnect layer to achieve various improvements in the etching of semiconductors. In U.S. Pat. Nos. 5,416,048 and 4,425,183, and as is further disclosed in U.S. Pat. No. 4,780,429, etched metallized features can further be provided with sloping sides to achieve various other improvements. The sloping sides resulting from such manufacturing processes are composed of oxides of the metals that form the metallized features of the IC, and they have been found to yield moderately high leakage currents, which can lead to undesirable short circuiting between adjacent metallized features.
U.S. Pat. No. 6,208,008 further suggests rounding the bottom corners of an etched metal structure, as seen from a sectional view of the metal layer. The methodology disclosed in this patent, however, requires several steps and results only in producing rounded bottom corners of the resulting etched metal structure.
SUMMARY OF THE INVENTION
Accordingly, to solve the above and other difficulties, the present invention is directed towards reducing the potential for cracking of a protective passivation layer utilized in an integrated circuit. In particular, the present invention reduces cracking in an overlying passivation layer by providing an interconnect layout that comprises rounded corners, as seen from a plan view of the metal layer.
Without wishing to be bound by theory, when a passivation layer is formed on or around an interconnect layer possessing such curvilinear corner geometry, it is believed that the stresses transferred to the passivation layer are significantly reduced, thereby reducing the potential for cracking of the passivation layer commonly experienced in prior art devices.
According to a first embodiment of the present invention, a method for improving the integrity of a passivation layer within an integrated circuit is provided. The method comprises: (1) identifying an integrated circuit comprising; (a) a substrate, (b) a patterned interconnect layer having at least one corner portion formed over the substrate, and (c) a passivation layer formed over at least one of the corner portions of the interconnect layer, the passivation layer exhibiting cracking at a position over at least one of the corner portions; and (2) modifying a patterned masking layer that is used in the formation of the patterned interconnect layer, such that the one or more corner portions under the passivation layer where cracking is exhibited are substituted with one or more curvilinear corner portions. Preferably, the integrated circuit is formed by a process comprising: (1) providing a metal layer over the substrate; (2) providing the patterned masking layer over the metal layer; (3) etching the metal layer through apertures in the patterned masking layer (preferably by an anisotropic etching process), thereby producing the interconnect layer; and (4) forming the passivation layer.
According to another embodiment of the invention, a method of improving the integrity of a passivation layer within an integrated circuit is provided, which comprises: (1) identifying an integrated circuit comprising; (a) a substrate, (b) a patterned interconnect layer disposed in a damascene trench formed in the substrate, the interconnect layer having at least one corner portion, and (c) a passivation layer formed over at least one of the corner portions of the interconnect layer, the passivation layer exhibiting cracking at a position over at least one of the corner portions; and (2) modifying a patterned masking layer used to form the damascene trench such that one or more of the corner portions under the passivation layer where the cracking is exhibited are substituted with one or more curvilinear corner portions. Preferably, the integrated circuit is formed by a process comprising: (1) providing the patterned masking layer over the substrate; (2) etching the substrate through apertures in the patterned masking layer, thereby producing the damascene trench; (3) forming the interconnect layer within the damascene trench; and (4) forming the passivation layer.
An advantage of the present invention is that it permits the manufacture of IC's having enhanced life expectancy and increased resistance to short-circuiting.
The above and other embodiments and advantages of the present invention will become immediately apparent to those of ordinary skill in the art upon review of the Detailed Description and Claims to follow.
REFERENCES:
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 4425183 (1984-01-01), Maheras et al.
patent: 4780429 (1988-10-01), Roche et al.
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5416048 (1995-05-01), Blalock et al.
patent: 5541425 (1996-07-01), Nishihara
patent: 5583381 (1996-12-01), Hara et al.
patent: 5866931 (1999-02-01), Bulucea et al.
patent: 6077789 (2000-06-01), Huang
patent: 6121149 (2000-09-01), Lukanc et al.
patent: 6208008 (2001-03-01), Arndt et al.
Amato John E.
Hshieh Fwu-Iuan
So Koon Chong
Bonham, Esq. David D.
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Powell William A.
LandOfFree
Integrated circuit resistant to the formation of cracks in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit resistant to the formation of cracks in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit resistant to the formation of cracks in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3112056