Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-14
2003-04-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185140, C365S185260
Reexamination Certificate
active
06549463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention is related to semiconductor nonvolatile memory and in particular to program and program verify for twin MONOS flash memories.
2. Description of Related Art
In MONOS flash memory devices, data is stored as electrons in the nitride region of an oxide-nitride-oxide (ONO) composite layer under a control gate. The presence of electrons in the nitride region increases the threshold of the device. An erased cell with a logical “1” stored has few or no stored electrons in the nitride region, and a programmed cell with a logical “0” stored has a fixed range of electrons in the nitride region. In conventional MONOS memories, the program operation is interrupted by program verify cycles in order to control the number of electrons in the nitride region. A state diagram of prior art for a program operation with program verify is shown in FIG.
1
. In the first program setup
101
is needed to startup the charge pumps and setup the voltages needed for the program operation. The selected memory cell is subjected to program voltage conditions during the program pulse step
102
. After a fixed time, the threshold of the memory cell is tested in the program verify step
103
. If the threshold of the memory cell is greater than the reference threshold, then the memory cell is deemed to have been programmed, and program is complete
104
. Otherwise if the threshold of the selected memory cell is not high enough, then the memory cell is placed back into the program state
102
.
FIG. 2
a
gives an example of voltage conditions of a MONOS memory cell of prior art for program and for program verify of prior art in
FIG. 2
b.
The memory cell is composed of a control gate
202
, a source
201
and a drain
203
. Electrons are stored in the nitride region
204
under the control gate
202
. It should be noted that the voltages that are shown are an example only. Actual voltages depend on many specifications such as program speed, oxide thickness, and memory cell dimensions. For CHE (channel hot electron) injection program, a voltage of approximately 10V is applied to the control gate
202
and another high voltage of approximately 5V is applied to the drain
203
with the source
201
grounded.
Referring to
FIG. 2
b,
program verify is very similar to a read operation, in that one diffusion will be measured with respect to a reference to determine the memory state. The control gate
202
is biased to approximately 2V, the drain
201
is biased to approximately 1V and the source
203
is biased to 0V.
Whenever there is a transition between program and program verify states, it is necessary to swap the source and drains and to lower the drain
203
voltage from 5V to 0V. If another program cycle is necessary, the drain
203
is raised to 5V again. This is an inefficient usage of charge, because extra current is needed to raise and lower the drain voltage between program and program verify cycles. When the drains of many memory cells are connected to a single highly capacitive bit line, the transition time between program and program verify increases. This increased transition time increases the overall program operation time.
FIG. 3
shows a prior art dual storage MONOS memory device (called NROM) in which there are two memory storage sites
304
and
305
within one memory cell, described in U.S. Pat. No. 6,011,725 (Eitan), which is directed to a method of read described called “reverse read”. The diffusion
303
, which is closest to the selected memory storage region
305
, becomes the lower voltage or source whereas the diffusion
301
, which is opposite the selected memory storage region
305
, becomes the higher voltage or drain. The drain voltage is higher than the source voltage in order to create a depletion region into the substrate and thus “override” the charge that may be stored in the unselected memory storage region, if it is in the high threshold “0” memory state. This type of NROM memory cell can only operate in reverse read mode, because a higher voltage is needed on the unselected memory storage side to override the unselected memory channel. If the device were to be read in the forward direction, then the higher drain voltage would override the selected memory storage side, and the cell would always be sensed to be in a low Vt “1” memory state.
Another prior art dual storage MONOS device is described in patent application Ser. No. 09/426,692, filed Oct. 25, 1999, called the twin MONOS cell and shown in
FIG. 4
a.
In this type of memory cell there are two extra side wall polysilicon control gate structures
406
and
407
in addition to the word gate
402
and two diffusions
401
and
403
. Unlike the control gate
302
of
FIG. 3
, the word gate
402
of
FIG. 4
a
does not have memory nitride storage regions underneath itself. Instead, the memory storage regions lie underneath the side wall polysilicon control gates
406
and
407
. As shown in
FIG. 4
a,
two side wall polysilicon gates between two adjacent memory cells are electrically connected together to define one equivalent control gate. Because the additional control gates
406
and
407
provide another level of flexibility, the twin MONOS cell can be easily read in both the reverse and forward directions. The channel underneath of the unselected nitride storage site can be overridden by increasing the voltage of the associated control gate to a voltage which is some delta above the highest possible threshold voltage (Vcg override). Although the twin MONOS cell is able to read in both directions, the forward read has slower read performance, due to lower cell current, smaller threshold margins, and limited voltage range.
FIG. 4
b
shows the relationship of drain voltage v.s. the threshold of the selected nitride region for memory nitride channel lengths of >50 nm and <50 nm. It can be seen that during forward read, the high Vt cell (“0”) suffers degradation of threshold at higher drain-source voltages. This effect becomes more severe for shorter channel lengths. Thus it is desirable to keep the drain voltage to lower than approximately 0.3~0.5V during sensing in order to maintain reasonable threshold margin between the “1” and “0” cell.
FIG. 4
c
is a schematic representation of the twin MONOS cell array in the diffusion bit configuration. Each memory cell consists of one word gate, two control gate halves, under which each control gate half is one nitride storage region, and two diffusion halves. In this array, memory cells are arranged in rows and columns, in which word gates are horizontally connected together by word lines WL[0-1], and bit diffusions are vertically connected together by bit lines BL[0-3], and control gates are vertically connected together by control lines CG[0-3]. Control lines CG[0-3] and bit lines BL[0-3] may run atop of one another and have a coupling capacitance of about 30%.
For high bandwidth program applications, it is desirable to program many memory cells in parallel. If many bit lines and control lines are need to be charged and discharged between program and program verify cycles, the voltage and current requirements of the charge pumps and voltage regulators will be very high, which impacts power and overall program time. In multi-level storage memories especially, the number of program and program verify cycles is greater in order to have tighter control between threshold states. Thus it is desirable to minimize the voltage transitions between program and program verify.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a low power method of programming a dual storage site MONOS memory cell.
It is also an objective of the present invention to provide a method of program verify for a dual storage site MONOS memory cell.
It is still an objective of the present invention to efficiently switch between program and program verify operations.
It is another objective of the present invention to minimize transition between program and progr
Ogura Nori
Ogura Seiki
Ogura Tomoko
Ackerman Stephen B.
Halo LSI, Inc.
Nelms David
Pham Ly Duy
Saile George O.
LandOfFree
Fast program to program verify method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast program to program verify method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast program to program verify method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3111953