Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2000-07-11
2003-06-03
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S349000, C257S354000
Reexamination Certificate
active
06573533
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device which is provided with MOS transistors formed on a semiconductor layer on an insulating layer and which can prevent supporting substrate stray effects.
2. Description of Related Art
A silicon-on-insulator (SOI) technology, which includes forming a semiconductor layer of single-crystal silicon on an insulator and forming semiconductor devices such as transistor devices on the semiconductor layer, has advantages, such as high-speed device operation, reduced electrical power consumption, and high integration density, and may be applied to electro-optical devices, such as liquid crystal devices.
In typical bulk semiconductor components, a channel region of a MOS transistor is maintained at a predetermined potential by an underlying supporting substrate. Thus, a parasitic bipolar effect due to a change in potential of the channel region does not cause deterioration of electrical characteristics, such as breakdown voltage of the device.
In a MOS transistor having an SOI structure, however, a channel bottom section is completely separated by an underlying insulating film. Thus, the channel region cannot be maintained at a predetermined potential, and is in an electrically straying state. In such a state, excessive carriers are accumulated in the channel bottom section in which the excessive carriers are generated by impact ionization due to collision of carriers accelerated in an electric field in the vicinity of a drain region with crystal lattices. When the channel potential increases by the accumulation of the excessive carriers in the channel bottom section, the NPN structure (in the case of N-channel type) of the source/channel/drain operates as an apparent bipolar device and yields an extraordinary current which causes deterioration of the breakdown voltage between the source and the drain, and thus, deterioration of electrical characteristics of the device. A series of phenomena caused by an electrical straying state of the channel region is called a supporting substrate stray effect.
A conventional method for suppressing the supporting substrate stray effect is providing a body contact region which is electrically connected to the channel region via a predetermined path in order to extract the excessive carriers in the channel region from the body contact region.
A semiconductor device including MOS transistors of an SOI structure having such a body contact region is disclosed in Japanese Unexamined Patent Application Publication No. 9-246562 (hereinafter Citation 1).
SUMMARY OF THE INVENTION
In a medium-breakdown-voltage MOS transistor used at approximately 15 volts in electro-optical devices such as liquid crystal devices, a semiconductor gate array including a plurality of the medium-breakdown-voltage MOS transistors, and a semiconductor device including a plurality of the medium-breakdown-voltage MOS transistors connected to each other in series, a high drain electric field generates a large amount of excessive carriers. Effective extraction of the excessive carriers is performed by increasing the impurity concentration in the extraction region to decrease the resistance of the extraction region. When the impurity concentration is increased in the structure of the Citation 1, the PN junctions between the extraction region and source/drain regions cannot withstand a high drive voltage.
It is an object of the present invention, for at least solving the above problems, to provide a semiconductor device provided with a MOS transistor formed on a semiconductor layer on an insulating layer which has junctions between the extraction region and the source/drain regions exhibiting a high breakdown voltage.
It is another object of the present invention to provide a semiconductor gate array including a plurality of the MOS transistors arranged on the semiconductor layer on the insulating layer.
It is another object of the present invention to provide a semiconductor device including a plurality of the MOS transistors which are formed on the semiconductor layer on the insulating layer and are connected to each other in series.
In an exemplary embodiment of the present invention, a semiconductor device preferably consists of a supporting substrate having insulation at least at a surface thereof, a semiconductor layer formed on the surface of the supporting substrate, and a MOS transistor formed in the semiconductor layer. The MOS transistor preferably consists of a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an second insulating layer formed on the channel region, and an electrode formed on the insulating layer. The semiconductor device may further consist of a first semiconductor region provided on the surface of the supporting substrate at least at one end in the channel width direction of at least one of the source region and the drain region along the channel length direction, and a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region. The second semiconductor region preferably has an impurity concentration which is higher than that in the channel region, and the first semiconductor region preferably has an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region having a low impurity concentration is provided between the second semiconductor region which is an extracting region of excessive carriers and the source and drain regions to suppress the gradient of the impurity concentrations between the second semiconductor region and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the second conductive type and may have an impurity concentration which is lower than that in the source region and the drain region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region of the second conductive type having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the first conductive type, and may have an impurity concentration which is lower than that in the second semiconductor region.
According to this configuration of this exemplary embodiment of the present invention, the first semiconductor region of the first conductive type having a low impurity concentration is provided between the second semiconductor region as an extracting region of the excessive carriers and the source and drain regions. Thus, the breakdown voltage of the junctions between the second semiconductor region and the source and drain regions may be maintained at a high level.
In another exemplary embodiment of the present invention, in the semiconductor device, the first semiconductor region may be a semiconductor of the first conductive type, and may have an impurity concentration which is substantially the same as that in the channel region.
According
Brock II Paul E
Oliff & Berridg,e PLC
Seiko Epson Corporation
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