Synchronizing circuit

Details Synchronizing circuit Synchronizing circuit

1991-12-18

1993-12-21

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307527, 328 63, 328 72, 328155, 375118, H03K 513, H03L 700

Patent

active

052723917

ABSTRACT:
A synchronizing circuit to synchronize a digital input signal (DIN) with a clock signal (CK1) includes a detection circuit (DC) which checks if a present (SA) sample of a clock signal (CK3) being synchronized with the digital input signal, is equal to the previous (SB) sample, both samples being taken at an interval equal to the period (T) of the clock signal synchronized with the output signal. When the samples differ, the detection circuit generates a phase adjustment signal (CLR), which triggers a phase adjustment circuit (PAC) to ensure a return to synchronism by phase shifting the signal (ES) controlling the sampling of the digital input signal.

REFERENCES:
patent: 4039960 (1977-08-01), Clark
patent: 4706033 (1987-11-01), Robidoux et al.
patent: 4873703 (1989-10-01), Crandall et al.
patent: 4965814 (1990-10-01), Yoshida et al.
patent: 5056120 (1991-10-01), Taniguchi et al.
patent: 5099477 (1992-03-01), Taniguchi et al.

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