Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-05-07
2003-08-26
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S111000, C438S112000, C438S121000
Reexamination Certificate
active
06610561
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to techniques effectively applicable to a lead-on-chip (LOC) semiconductor device.
The LOC package is one of surface-mount LSI packages. In the LOC package, inner lead parts of leads are arranged on an insulating film formed on a major surface of a semiconductor chip, and the inner lead parts are connected electrically to the bonding pads of the semiconductor chip with Au wires. The insulating film is formed of a heat-resistant resin, such as a polyimide resin. The opposite surfaces are coated with an adhesive.
A LOC package of this kind is disclosed in Japanese Patent Laid-Open No. Hei 2-246125.
SUMMARY OF THE INVENTION
The foregoing LOC package has the insulating film of a thickness on the order of 50 &mgr;m interposed between the semiconductor chip and the inner lead parts. This insulating film is an obstacle to fabricating a very thin package of a thickness on the order of 1 mm. Furthermore, the insulating film is costly and requires work for applying the same to a lead frame, which increases the manufacturing costs of the package.
Furthermore, the insulating film has a hygroscopic property higher than that of a resin forming the package. Therefore, it is possible that the package is cracked by steam produced by the sudden evaporation and expansion of moisture absorbed by the insulating film caused by heat applied to the package during temperature cycling tests or heat applied to the package when soldering the package to a printed wiring board.
Accordingly, it is a first object of the present invention to provide techniques capable of fabricating thin LOC packages.
A second object of the present invention it to provide techniques capable of fabricating LOC packages at a low manufacturing cost.
A third object of the present invention is to provide techniques capable of improving the reliability of LOC packages and of improving the yield of a LOC package producing line.
Among inventions disclosed in this application, the outline of representative ones will be briefly described as follows.
(1) According to a first aspect of the present invention, a semiconductor package comprises: a semiconductor chip provided with a plurality of bonding pads formed on a major surface thereof; a power lead extended along a direction in which the bonding pads are arranged and having a depressed portion depressed toward the major surface of the semiconductor chip; and a signal lead having an end part lying in a region corresponding to the major surface of the semiconductor chip; wherein the power lead and the signal lead are connected electrically to the bonding pads by a bonding wire, the depressed portion of the power lead is fixed to the major surface of the semiconductor chip by an adhesive layer, and the signal lead is spaced apart from the major surface of the semiconductor chip.
(2) In the semiconductor device stated in (1), the power lead includes a first power lead for applying a supply voltage to the semiconductor chip, and a second power lead for applying a reference voltage to the semiconductor chip, and the first and the second power leads are disposed on the opposite sides of the arrangement of the bonding pads, respectively.
(3) In the semiconductor device stated in (1), the distance between the signal lead and the major surface of the semiconductor chip is greater than the distance between the power lead and the major surface of the semiconductor chip.
(4) In the semiconductor device stated in (1), the depressed portion of the power lead is positioned inside the ends of the semiconductor chip.
(5) In the semiconductor device stated in (1), parts of the power lead and the signal lead corresponding to the end parts of the semiconductor chip are spaced a distance not shorter than 10 &mgr;m apart from the major surface of the semiconductor chip.
(6) In the semiconductor device stated in (1), the adhesive layer is formed of a thermoplastic adhesive.
(7) In the semiconductor device stated in (1), the signal lead is disposed farther from the bonding pads than the power lead, and the bonding wire electrically connecting the signal lead to the bonding pads is extended over the power lead.
(8) In the semiconductor device stated in (1), the power lead have a bend bent in a plane parallel to the major surface of the semiconductor chip, respectively.
(9) In the semiconductor device stated in (1), the major surface of the semiconductor chip is coated with a protective film, and power supply lines electrically connected to the power lead underlie the protective film.
(10) In the semiconductor device stated in (1), an insulating layer for absorbing shocks that may be exerted on the semiconductor chip during a wire bonding operation is formed on the major surface of the semiconductor chip excluding regions in which the bonding pads are formed.
(11) In the semiconductor device stated in (1), the semiconductor chip, the inner lead part of the power lead and the inner lead part of the signal lead are sealed in a resin package, the outer lead part of the power lead and the outer lead part of the signal lead project outside from the resin package.
(12) According to a second aspect of the present invention, a semiconductor device comprises: a semiconductor chip provided with a plurality of bonding pads formed on a major surface thereof; power leads connected extended along a direction in which the bonding pads are arranged, and having depressed portions depressed toward the major surface of the semiconductor chip; and signal leads having end parts lying in a region corresponding to the major surface of the semiconductor chip; wherein the power leads and the signal leads are connected electrically to the bonding pads by bonding wires, respectively, the depressed portions of the power leads are fixed to the major surface of the semiconductor chip by an adhesive layer, and the signal leads are spaced apart from the major surface of the semiconductor chip.
(13) In the semiconductor device stated in (12), the power leads include a first power lead for applying a supply voltage to the semiconductor chip, and a second power lead for applying a reference voltage to the semiconductor chip, and the first and the second power leads are disposed on the opposite sides of the arrangement of the bonding pads, respectively.
(14) In the semiconductor device stated in (12), projections project from parts of the leads extending along the direction in which the bonding pads are arranged in a direction away from the bonding pads, one end of each of the bonding wires electrically connecting the power leads to the bonding pads is bonded to the projection.
(15) In the semiconductor device stated in (12), a branch lead extends near the semiconductor chip from parts of the power leads, one end of each of the bonding wires electrically connecting the power leads to the bonding pads is bonded to the branch lead.
(16) According to a third aspect of the present invention, a semiconductor device comprises: a semiconductor chip provided with a plurality of bonding pads formed on a major surface thereof; a power lead arranged along a direction in which the bonding pads are arranged and having a part fixed to the major surface of the semiconductor chip by an adhesive layer; and a signal lead having a part lying in a region corresponding to the major surface of the semiconductor chip; wherein the power lead and the signal lead are connected electrically to the bonding pads by bonding wire, and the signal lead is spaced apart from the major surface of the semiconductor chip.
(17) In the semiconductor device stated in (16), the adhesive layer is extended in substantially all regions underlying the power lead.
(18) In the semiconductor device stated in (16), the adhesive layer is extended in part of regions underlying the power lead.
(19) In the semiconductor device stated in (16), the adhesive layer is extended in regions underlying bonding parts of the power lead.
(20
Imura Chikako
Iwaya Akihiko
Masuda Masachika
Nakamura Atsushi
Shiotsuki Toshihiro
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Picardat Kevin M.
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