Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
1999-06-11
2003-12-09
Jones, Hugh (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C716S030000
Reexamination Certificate
active
06662145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for controlling exposure accuracy, and more specifically to a method, equipment, and a recording medium for forming highly accurate resist patterns of a resolution limit level on a aligner.
2. Description of Related Art
In recent years, the dimensions of resist patterns to be formed in an aligner have been decreased to 0.2 &mgr;m or even smaller. Since these dimensions are smaller than the wavelengths of light used for exposing the resist patterns, the use of special methods such as the use of deformed illumination or half-tone masks is required if resolution must be improved.
However, since deformed illumination is a method for further resolving a resist pattern with regular pitches, the resolution of an isolated pattern with irregular pitches, or having dense and sparse portions, is poor. Furthermore, since a half-tone mask is generally expensive, the use of half-tone masks elevates the costs for forming resist patterns. Therefore, even by these methods, the resolution of irregular resist patterns is difficult.
As a method for solving the above problems, the double exposure method disclosed in Japanese Patent Application Laid Open No. 5-234851 has been proposed.
FIG. 5
shows the conventional double exposure method disclosed in the above patent application. In
FIG. 5
, the first exposure is carried out by radiating light beams
3
from the light source onto a substrate
1
on which a photoresist film has been formed placed on an XY-stage
12
through a mirror
9
, a lens
10
, and a converging lens
11
. Then the second exposure is carried out by using light beams of which phase is shifted by 180 degrees from the light beams used in the first exposure. The phase is shifted by 180 degrees by inserting a phase shifting plate
5
underneath a reticule
4
. A resist pattern is formed by two types of light beams having phases shifted by 180 degrees from each other for improving resolution.
However, in order to prevent the misalignment of the resist pattern by this method, the insertion and withdrawal of the phase shifting plate
5
are required for each exposure, causing the throughput to be lowered.
Another method is a positioning method disclosed in Japanese Patent Application Laid-Open No. 61-44429.
FIG. 6
shows the conventional positioning method disclosed in the above patent application (EGA measurement method). The positioning method shown in
FIG. 6
is a method for minimizing the difference between the measured value of each point when the resist pattern is aligned to the reference position on the wafer and the true coordinate value on the wafer statistically using the least square method. In
FIG. 6
, the reticule
23
, which is a master plate, has been positioned so that the center of projection passes the optical axis AX of the projecting lens
21
. The projecting lens
21
projects the circuit pattern drawn on the reticule
23
onto the wafer
20
on the wafer holder
22
. The laser beam LB is incident on the beam splitter
30
, and a part reaches the wafer
20
through the mirror
31
and the projecting lens
21
, and forms an image as a spot light LYS. The laser beam split toward the other mirror
41
forms an image as a spot light LXS. Spot lights LYS and LXS scan the mark
29
on the wafer in the y and x directions, respectively. When the spot lights LYS and LXS scan the mark
29
, a diffracted light is produced. This diffracted light is reflected, condensed, converted to an optoelectric signal, and transmitted to the controller
27
. The controller
27
stores the position information of the mark
29
, and after computation for positioning based on the transmitted signal, it positions the wafer
20
by driving motors
24
,
25
, and
26
.
A method for double exposure is also considered in which the misalignment of the shot for the wafer is monitored before exposure using a conventional EGA measurement method as described above, and double exposure is carried out based on the monitored measurement data. However, since the position accuracy when double exposure is carried out is presently said to be ±50 nm, if the conventional EGA measurement method is used for double exposure, about 25% of the dimension (50 nm/0.2 &mgr;m) will be shifted. Considering that the demand for the final dimensional accuracy is around ±30 nm, the dimensional accuracy for each of double exposure should be around ±15 nm. Therefore, even if the conventional EGA measurement method is used for double exposure, there is a problem that dimensional accuracy does not fall within a practical level.
As described above, conventional double exposure methods have a problem in that the insertion and withdrawal of the phase shifting plate are required for each exposure, causing the throughput to be lowered. Also, the double exposure method based on measured data monitored before exposure using the EGA measurement method has a problem in that the dimensional accuracy does not fall within a practical level.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method, equipment, and recording medium for increasing dimensional accuracy to around ±15 nm by double exposure by changing optical conditions.
According to a first aspect of the present invention, there is provided a method of controlling exposure accuracy comprising: a step of placing a wafer on the wafer scan stage of an aligner; a step of placing a reticle on the reticle scan stage of said aligner; a step of positioning said reticle; a first exposure step for exposing said wafer while setting the exposure to a quantity for a dense resist pattern; a cleaning step for restoring the elongation of said wafer; and a second exposure step for exposing said wafer while setting the exposure to a quantity for a sparse resist pattern.
According to a second aspect of the present invention, there is provided an equipment of controlling exposure accuracy controlling the accuracy of exposure for wafers comprising: a first measurement means for measuring the coordinates established on said wafer, and the coordinates of the positions of the resist pattern when said resist pattern is aligned to the alignment mark formed on the underlying pattern of said wafer; a first exposure instruction means instructing exposure of said wafer while setting the exposure to a quantity for a dense resist pattern based on data obtained from said first measurement means; a means for instructing the cleaning for restoring the elongation of said wafer; a second measurement means for measuring the coordinates established on said wafer, and the coordinates of the positions of the resist pattern when said resist pattern is aligned to the alignment mark formed on the underlying pattern of said wafer; and a second exposure instruction means instructing exposure of said wafer while setting the ratio of exposure to total exposure to be larger than a the ratio of exposure to total exposure for a dense resist pattern based on data obtained from said second measurement means.
According to a third aspect of the present invention, there is provided a computer-readable recording medium of recording a program for executing the method of controlling exposure accuracy comprising: a step of placing a wafer on the wafer scan stage of an aligner; a step of placing a reticle on the reticle scan stage of said aligner; a step of positioning said reticle; a first exposure step for exposing said wafer while setting the exposure to a quantity for a dense resist pattern; a cleaning step for restoring the elongation of said wafer; and a second exposure step for exposing said wafer while setting the exposure to a quantity for a sparse resist pattern.
REFERENCES:
patent: 5100508 (1992-03-01), Yoshida et al.
patent: 5243377 (1993-09-01), Umatate et al.
patent: 5937290 (1999-08-01), Sekiguchi et al.
patent: 6150256 (2000-11-01), Furukawa et al.
patent: 6159644 (2000-12-01), Satoh et al.
patent: 6211528 (2001-04-01), Tamura
patent: 6312863 (2001-11-01),
Garcia-Otero Eduardo
Jones Hugh
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