Electrical computers and digital processing systems: multicomput – Distributed data processing
Reexamination Certificate
1999-11-09
2003-12-30
Alam, Hosain T. (Department: 2155)
Electrical computers and digital processing systems: multicomput
Distributed data processing
C709S218000, C709S223000, C709S248000, C709S253000
Reexamination Certificate
active
06671712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and, in particular, to an interconnect of a data processing system. Still more particularly, the present invention relates to a multi-node data processing system having a non-hierarchical interconnect architecture.
2. Description of the Related Art
It is well-known in the computer arts that greater computer system performance can be achieved by harnessing the processing power of multiple individual processors in tandem. Multi-processor (MP) computer systems can be designed with a number of different architectures, of which various ones may be better suited for particular applications depending upon the intended design point, the system's performance requirements, and the software environment of each application. Known architectures include, for example, the symmetric multiprocessor (SMP) and non-uniform memory access (NUMA) architectures. Until the present invention, it has generally been assumed that greater scalability and hence greater performance is obtained by designing more hierarchical computer systems, that is, computer systems having more layers of interconnects and fewer processor connections per interconnect.
The present invention recognizes, however, that such hierarchical computer systems incur extremely high communication latency for the percentage of data requests and other transactions that must be communicated between processors coupled to different interconnects. For example, even for the relatively simple case of an 8-way SMP system in which four processors present in each of two nodes are coupled by an upper level bus and the two nodes are themselves coupled by a lower level bus, communication of a data request between processors in different nodes will incur bus acquisition and other transaction-related latency at each of three buses. Because such latencies are only compounded by increasing the depth of the interconnect hierarchy, the present invention recognizes that it would be desirable and advantageous to provide an improved data processing system architecture having reduced latency for transaction between physically remote processors.
SUMMARY OF THE INVENTION
The present invention realizes the above and other advantages in a multi-node data processing system having a non-hierarchical interconnect architecture.
In accordance with the present invention, a data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The nodes are coupled by an interconnect including a plurality of address channels to which each agent is coupled and at least one data channel. Each agent can only issue transactions on an associated address channel. However, agents snoop transactions on all of the plurality of address channels.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Arimilli Ravi Kumar
Fields, Jr. James Stephen
Guthrie Guy Lynn
Joyner Jody Bern
Lewis Jerry Don
Alam Hosain T.
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Salys Casimer K.
Won Young N
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