Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes
Reexamination Certificate
2001-12-31
2003-06-03
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from variable length codes
Reexamination Certificate
active
06573846
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to data processing systems using vector processing and Very Long Instruction Word (VLIW) architecture, more particularly to variable length decoding and encoding of bit streams.
BACKGROUND OF THE INVENTION
FIG. 3
shows a typical computer system having at least one host processor
1301
and host memory
1302
. The system core logic chip
1300
, also known as a memory controller or a north bridge, facilitates data transfer between the host memory
1302
through a memory interface
1304
, the host processor
1301
through a host interface
1303
, graphics controller
1308
through a PCI-0/AGP interface
1306
and other peripherals such as input/output (I/O) controller
1309
through PCI-1 interface
1307
. An IEEE-1394 bus
1310
, also known as a FireWire bus, may be coupled to the I/O controller
1309
. The FireWire bus
1310
, in some applications, may be directly coupled to the system core logic chip
1300
through the PCI-1 interface
1307
. The FireWire bus
1310
provides interfaces to other FireWire devices, such as FireWire storage devices (e.g., FireWire hard disks). Other components such as universal serial bus (USB), Ethernet device, etc., may be coupled to the system core logic
1300
. Due to these interfaces, the system core logic
1300
requires a large number of pins. On the other hand, the logic required for the system core logic functions is relatively small. The large number of interface pins causes the area of the system core logic
1300
to become quite large. The small amount of logic combined with continuing advancement in silicon technology, results in the significant portion of that area being unused.
The concept of a media processor has been around for a while. A media processor typically refers to an engine designed for the processing of a combination of audio, video and graphics data. A media processor can also be used for other tasks that require similar processing features. The media processors have so far been designed as stand-alone processors and have enjoyed moderate success in processing video data. The media processors can be used in add-in boards to perform various tasks.
FIG. 4A
shows an example of a conventional media processor in a computer system. The system
1400
of
FIG. 4A
includes a host processor or processors
1401
, host memory
1402
, a graphics controller
1404
, and a media processor
1405
. The bus
1403
interconnects these various components together. Other peripherals may be connected to the bus
1403
.
FIG. 5A
shows an example of a conventional media processor. The media processor
1500
includes an input/output (I/O) interface, which receives and transmits data between the media processor and other components of the system, such as host processor and host memory
1506
. The media processor
1500
may also include a cache memory
1504
for temporarily storing data before the instruction decoder
1502
decodes the instructions and transmits them to different functional units, such as vector processors
1503
. The media processor
1500
may include one or more register files for storing input or output data of the functional execution units
1503
.
A media processor may employ multiple functional units (e.g., adder, multiplier, shift, load/store units), and use very long instruction word (VLIW) programming. Depending on the target application, the media processor may have a combination of functional units of different kind and there may be more or fewer of these units. Some media processors only integrate vector-processing units (e.g., vector processors). Vector processors allow execution of a single instruction on multiple data elements. There are several vector processors available on the market (e.g., Motorola's AltiVec, SSE-2, etc.). The conventional media processors use the scalar processing unit available through the host processors. Thus, the vector data are processed by the vector processing units and the scalar data are processed by the scalar processing units through the host system. This arrangement may require the data to be transferred between the host system and the media processor, thus it may impact performance.
The conventional media processor may use very long instruction word (VLIW) programming. Depending on the target application, the media processor may have a combination of functional units of different kind and there may be more or few of the functional units. The VLIW contains one instruction slot for each of these units. The VLIW programming is based on issuing instructions to all of these functional units in the same clock cycle of the host processor. Not all instructions may need to be issued on each clock cycle. If an instruction slot in the VLIW instruction is not used in a particular cycle, it is assigned a code of no-operation (NOOP), but it still occupies bits in the VLIW instruction. This results in code expansion and therefore in memory, bandwidth, and instruction cache related inefficiencies.
Typically, a graphics controller may be coupled to the PCI bus. PCI bus supports multiple peripheral components and add-in cards at a peak bandwidth of 132 megabytes per second. Thus, PCI is capable of supporting full motion video playback at 30 frames per second, true color high-resolution graphics and 100 megabytes per second Ethernet local area networks. However, the emergence of high-bandwidth applications, such as three-dimensional (3-D) graphics applications, threatens to overload the PCI bus. As a result, a dedicated graphics bus slot, known as an accelerated graphics port (AGP), has been designed and integrated into the computer system, such as AGP interface
1306
of FIG.
3
. AGP operates at higher frequency and transfers data at a rate up to 1 GB/sec. AGP's greater bandwidth will allow game and 3D application developers to store and retrieve larger, more realistic textures in system memory rather than video memory, without incurring a dramatic performance hit to the rest of the system.
Many computer systems, such as system
1300
of
FIG. 3
, use virtual memory systems to permit the host processor
1301
to address more memory than is physically present in the main memory
1302
. A virtual memory system allows addressing of very large amounts of memory as though all of that memory were a part of the main memory of the computer system. A virtual memory system allows this even though actual main memory may consist of some substantially lesser amount of storage space than is addressable.
As a result, a system with a graphics accelerator connected to the AGP port of the system core logic normally requires graphics address re-mapping table (GART) to translate a virtual address space to the physical address. However, since the AGP address ranges are designed dedicated to the AGP accelerator, it is a fixed memory range that may not be shared with other components in the system.
In addition, the media processor in an AGP system normally uses mapped non-coherent memory access. Non-coherent memory operations are those operations where data goes directly to and from memory and is returned directly back to the media processor and never goes through the processor cache. On the other hand, a coherent memory system always goes through the host processor. The data of a coherent memory system may exist in the host processor's cache or in the host memory. Referring to
FIG. 3
, when a coherent memory access request is issued, the host processor
1301
checks whether the host processor's cache (not shown) contains newer data than the host memory
1302
. If the host processor cache contains newer data, the host processor
1301
flushes its caches into the host memory
1302
before the data is read from the host memory. Lack of coherent access of the conventional approaches posts an inconvenience to the applications.
As graphics data processing is getting more complex, improvements in media data processing systems increase the ability to handle more complex processing.
Many applications, such as motion estimation for video images compressed in
Ouzilevski Alexei V.
Sarwar Mushtaq A.
Takahashi Yutaka
Trivedi Sushma Shrikant
Apple Computer Inc.
Blakely , Sokoloff, Taylor & Zafman LLP
Young Brian
LandOfFree
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