Optics: measuring and testing – Shape or surface configuration
Reexamination Certificate
2001-12-13
2003-08-19
Font, Frank G. (Department: 2877)
Optics: measuring and testing
Shape or surface configuration
C356S237500
Reexamination Certificate
active
06608686
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to measuring the thickness and profiles of metal layers in an integrated circuit. A key application is the measurement of metal electroplating barrier and seed layers.
BACKGROUND
One of the key metrology problems for thin metal layers is the measurement of metal thickness and profile in the actual line or contact (or via). Many times, measurements are made in a field or flat area away from the actual area of the line. These measurements do not necessarily give an accurate estimation of the film thickness or profile within the actual line area. One particular case involves copper metallization. For copper metallization it is necessary to measure the barrier, typically tantalum (Ta) or tantalum nitride (TaN), and seed layers (typically Cu) which are deposited before copper electroplating. These layers are deposited on patterned (often called Damascene) structures. Due to typical non-conformality of processes used to deposit these layers (typically physical vapor deposition or PVD), the thickness of these films on the surface is very different (much thicker) from the thickness on the sidewall and bottom of the trench or via. Thickness of the barrier is typically around 20-40 nm on the surface and only 5-10 nm on the sidewall. Copper seed thickness is 50-150 nm on the surface and 10-25 nm on the sidewall.
The sidewall thickness is critical for two reasons. First, the side wall thickness determines the integrity of the barrier layer, which must be thick enough to prevent metal diffusion. Second, in order for electroplating to completely fill a structure, the seed layer needs to be continuous. If the seed metal layer is too thin on the sidewall, filling will be incomplete, resulting in voids. Other problems can be caused when the seed layer is thicker at the top of a damascene structure than at the bottom. This can result in pinch-of of the filling during plating, again resulting in voids.
After metal electroplating is used to fill the entire damascene structure, all metal is removed from the wafer surface. This means that what is currently being measured on the field area is not really relevant. IC manufacturers are interested in the thickness of these materials on the sidewall, but can only measure the material on the surface non-destructively. Currently, in order to measure the material on the sidewalls, it is necessary to do cross-sectional scanning electron microscopes (SEM's) or transmission electron microscope (TEM's), thereby necessitating “breaking the wafer.”
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Jakatdar Nickhil
Lane Lawrence
Niu Xinhui
Morrison & Foerster / LLP
Nguyen Sang H.
Timbre Technologies, Inc.
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