Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1997-12-23
2003-04-01
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C375S229000, C375S230000, C370S286000, C708S300000
Reexamination Certificate
active
06542539
ABSTRACT:
TECHNICAL FIELD
This invention relates to finite impulse response (FIR) filters, and more particularly, to adaptive FIR filters using time multiplexed multipliers with multiple coefficients per multiplier.
BACKGROUND OF THE INVENTION
Prior art adaptive finite impulse response (FIR) filters employ fixed delay lines for recirculating the coefficients. Such delay lines are implemented using a series of edge triggered flip flops. As a result, in operation, the prior art delay lines consume more power than is desirable.
In copending U.S. patent application Ser. No. 08/937665, assigned to the same assignee as the instant application, multiported register files are employed to implement the coefficient storage and to provide the delays in the coefficients that are necessary for filter operation. A multiported register file is a memory, typically small, e.g., having a capacity for four words, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register file may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port. In regards to coefficients, each multiported register file feeds data from one output port to the multiply-add portion of its associated stage of the FIR filter. In regards to an adaptive filter, each multiported register file feeds data from another output to the update unit for that coefficient. Note that these output ports may be the same, and if not, the data supplied to them may be the same. For coefficient use, there is no need to operate the multiported register file in the lookthrough mode described in the copending application.
When the FIR filter is an adaptive filter with updatable coefficients, it is necessary to have an update unit which computes new coefficient values. Such an update unit incorporates, or is associated with, an overflow/underflow detection and/or saturation unit, which is used in the prevention of catastrophic errors in the filter that could occur when overflow or underflow takes place. Such errors can occur because of the nature of conventional techniques for performing arithmetic using binary numbers. For example, when two large positive numbers represented using two's complement representation are added the result could appear to be a negative number, which clearly is erroneous. An overflow/underflow detection unit and/or saturation prevents this problem by supplying as an output, depending upon its incarnation, one of the following: a) flags indicating whether overflow or underflow has occurred; b) a value representing the maximum positive or negative number that can be represented as a saturation value; or c) the actual result of the calculation. This overflow/underflow detection and/or saturation unit lies in the critical path of coefficient updating circuitry, i.e., it is in the path that determines the maximum speed at which the updating can be performed. Thus, the speed at which the overflow/underflow detection and/or saturation process can be performed limits the speed of the updating process.
SUMMARY OF THE INVENTION
We have recognized that improved multiported register files may be used for storing coefficients in adaptive FIR filters. In accordance with the principles of the invention, the multiported register files of the prior copending application are improved by incorporating therein computational ability, e.g., the ability to perform computation on coefficient values or derivatives thereof, or to control the operations performed thereon. In accordance with one aspect of the multiported register file incorporates therein an overflow/underflow detection and/or saturation unit. In accordance with another aspect of the invention, the multiported register file incorporates therein a special encoder which is used to speed up the multiplication process, e.g., the so-called “Booth” encoder. In accordance with another aspect of the invention, the multiported register file incorporates therein a converter for changing the representation of the coefficients, e.g., a two's complement to sign-magnitude converter. In accordance with an aspect of the invention, all computation performed in the multiported register file is performed outside of the critical path of the filtering or of the coefficient updating. Advantageously, using such improved multiported register files, adaptive FIR filters can be constructed which operate faster, and with lower power consumption, than those of the prior copending application.
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Weste, Neil H.E. and Eshraghian, Kamran, Principles of CMOS VLSI Design—A Systems Perspectives, 2nd ed., Addison-Wesley Publishing Company, p. 19-21. and 547-554.
Larsson Patrik
Nicol Christopher John
Agere Systems Guardian Corp.
Chin Stephen
Liu Shuwang
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